VL6524 datasheet(33/70 Pages) STMICROELECTRONICS

33 / 70 page

VL6524/VS6524

Host communication - I²C control interface

33/70

For the master reading from the slave the device address is followed by the contents of last

read then the internal register index is automatically incremented after each byte of data

read. A read message is terminated by the bus master generating a negative acknowledge

after reading a final byte of data.

A message can only be terminated by the bus master, either by issuing a stop condition, a

repeated start condition or by a negative acknowledge after reading a complete byte during

a read operation.

Detailed overview of the message format

Figure 19.

Detailed overview of message format

The V2W generic message format consists of the following sequence

Master generates a START condition to signal the start of new message.

Master outputs, MS bit first, a 7-bit device address of the slave the master is trying to

communicate with followed by a R/W bit.

SDA

SCL

MSB

LSB

START

repeated

START

condition

ACK

signal

from

slave

STOP

repeated

Start

condition

Device Address

MSB

LSB

(Sr)

7-bit Device

Address

R/W

(A)

8-bit Data

(Sr)

Data byte from

transmitter

R/W=0 - Master

R/W=1 - Slave

ACK

signal

from

receiver

R/W

Bit

0 - Write

1 - Read

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