VL6524 datasheet(16/70 Pages) STMICROELECTRONICS

16 / 70 page

Clock control

VL6524/VS6524

16/70

Clock control

5.1

Input clock

The VL6524/VS6524 contains an internal PLL allowing it to produce accurate frame rates

from a wide range of input clock frequencies. The allowable input range is from 6.5 MHz to

26 MHz. The input clock frequency must be programmed in the

uwExtClockFreqNum

(MSB), uwExtClockFreqNum (LSB) and bExtClockFreqDen registers (Table 12). To program

an input frequency of 6.5 MHz, the numerator can be set to 13 and the denominator to 2.

The default input frequency is 12 MHz.

5.2

System clock division

It is possible to set an overall system clock division of 2 in the

bEnableGlobalSystemClockDivision register (Table 12). This results in a PCLK of 12MHz

and a maximum frame rate of 15fps VGA.

5.3

Pixel clock (PCLK)

All data output from the VL6524/VS6524 is qualified by the PCLK output. The PCLK

frequency is 24 MHz (equivalent to a 12 MHz pixel rate as each pixel is represented by 2

bytes of data). For frame rates less than 30 fps the PCLK frequency is not reduced, instead

additional interframe lines are added into the output data stream.

Figure 4.

Frame output format against framerate

Interframe Blanking

1/30 sec

Interframe Blanking

1/15 sec

Frame output 15fps

Frame output 30fps

Interline

Blanking

Interline

Blanking

ACTIVE VIDEO

Interline

Blanking

ACTIVE VIDEO

Interline

Blanking

ACTIVE VIDEO

Interline

Blanking

ACTIVE VIDEO

VL6524 Folha de dados(PDF) 16 Page - STMicroelectronics

VL6524 Folha de dados(HTML) 16 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Folha de dados Download

Ligação URL