LTC4260IGN datasheet(18/28 Pages) LINER

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LTC4260

4260f

R/W bit now set to one. The LTC4260 acknowledges and

sends the contents of the requested register. The trans-

mission is ended when the master sends a STOP condi-

tion. If the master acknowledges the transmitted data byte,

as in a Read Word command, the LTC4260 will repeat the

requested register as the second data byte.

Note that the Register Address pointer is not cleared at the

end of the transaction. Thus the Receive Byte protocol can

be used to repeatedly read a specific register.

Alert Response Protocol

The LTC4260 implements the SMBus Alert Response

Protocol as shown in Figure 11. If enabled to do so through

the ALERT register B, the LTC4260 will respond to faults

by pulling the ALERT pin low. Multiple LTC4260s can

share a common ALERT line and the protocol allows a

master to determine which LTC4260s are pulling the line

low. The master begins by sending a START bit followed

by the special Alert Response Address (0001 100)b with

the R/W bit set to one. Any LTC4260 that is pulling its

ALERT pin low will acknowledge and begin sending back

its individual slave address.

An arbitration scheme ensures that the LTC4260 with the

lowest address will have priority; all others will abort their

response. The successful responder will then release its

ALERT pin while any others will continue to hold their

ALERT pins low. Polling may also be used to search for any

LTC4260 that have detected faults. Any LTC4260 pulling

its ALERT pin low will also release it if it is individually

addressed during a read or write transaction.

The ALERT signal will not be pulled low again until the

FAULT register indicates a different fault has occurred or

the original fault is cleared and it occurs again. Note that

this means repeated or continuing faults will not generate

alerts until the associated FAULT register bit has been

cleared.

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

1 - 7

4260 F06

a6 - a0

b7 - b0

1 - 7

Figure 6. Data Transfer Over I2C or SMBus

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