LTC4260IGN datasheet(12/28 Pages) LINER

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LTC4260

4260f

APPLICATIO S I FOR ATIO

As the SOURCE voltage rises, so will the FB pin which is

monitoring it. If the voltage across the current sense

resistor RS gets too high, the inrush current will then be

limited by the internal current limit circuitry. Once the FB

pin crosses its 3.5V threshold, the GPIO pin, in its default

configuration, will cease to pull low and indicate that the

power is now good.

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A

normal turn-off is initiated by the ON pin going low or a

serial bus turn-off command. Additionally, several fault

conditions will turn off the switch. These include an input

overvoltage (OV pin), input undervoltage (UV pin), over-

current circuit breaker (SENSE pin) or BD_PRST going

high. Writing a logic one into the UV, OV or overcurrent

fault bits will also turn off the switch if their autoretry bits

are set to false.

Normally the switch is turned off with a 1mA current

pulling down the GATE pin to ground. With the switch

turned off, the SOURCE voltage drops and when the FB pin

crosses below its threshold, GPIO pulls low to indicate

that the output power is no longer good.

If the VDD pin falls below 7.5V for greater than 5µs or

INTVCC drops below 3.8V for greater than 1µs, a fast

shutdown of the switch is initiated. The GATE pin is pulled

down with a 600mA current to the SOURCE pin.

Overcurrent Fault

The LTC4260 features an adjustable current limit with

foldback that protects against short circuits or excessive

load current. To protect against excessive power dissipa-

tion in the switch during active current limit, the available

current is reduced as a function of the output voltage

sensed by the FB pin. The device also features a variable

overcurrent response time. A graph in the Typical Perfor-

mance curves shows the delay from a voltage step at the

SENSE pin until the GATE voltage starts falling, as a

function of overdrive.

An overcurrent fault occurs when the current limit circuitry

has been engaged for longer than the time-out delay set by

the TIMER pin. Current limiting begins when the current

sense voltage between the VDD and SENSE pins reaches

20mV to 50mV (depending on the foldback). The GATE pin

is then brought down with a 600mA GATE-to-SOURCE

current. The voltage on the GATE is regulated in order to

limit the current sense voltage to less than 50mV. At this

point, a circuit breaker time delay starts by charging the

external timing capacitor from the TIMER pin with a 100µA

pull-up current. If the TIMER pin reaches its 1.2V thresh-

old, the external switch turns off (with a 1mA current from

GATE to ground). The overcurrent present bit, C2, and the

overcurrent fault bit, D2, are set at this time.

The circuit breaker time delay is given by:

tCB = CT • 12 [ms/µF]

After the switch is turned off, the TIMER pin begins

discharging the timing capacitor with a 2µA pull-down

current. When the TIMER pin reaches its 0.2V threshold,

the overcurrent present bit, C2, is cleared, and the switch

will be allowed to turn on again if the overcurrent fault has

been cleared. However, if the overcurrent autoretry bit,

A2, has been set then the switch turns on again automati-

cally (without resetting the overcurrent fault). Use a mini-

mum value of 0.1nF for CT.

The waveform in Figure 3 shows how the output latches off

following a short circuit. The drop across the sense

resistor is held at 20mV as the timer ramps up.

Figure 2. Supply Turn-On

VDD + 13V

VDD

4260 F02

GATE

VOUT

SLOPE = 18µA/C1

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