P9221-R3 datasheet(6/46 Pages) RENESAS

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P9221-R3 Datasheet

October 20, 2017

2. Pin Descriptions

Table 1.

Pin Descriptions

Pins

Name

Type

Function

COMM1

Output

Open-drain output used to communicate with the transmitter. Connect a 47nF capacitor

from AC1 to COMM1.

ALIGNX

Input

AC input for coil alignment guide. If not used, connect this pin to GND through a 10kΩ

resistor.

SCL

Input

Serial clock line. Open-drain pin. Connect this pin to a 5.1kΩ resistor to the VDD18 pin.

VOSET/

Q-Fact

Input

Programming pin for setting the output voltage and Q-factor. For VOSET, connect this pin

to the center tap of a resistor divider to set the output voltage. For more information, refer

to section 8.2 for different output voltage settings. Also see section 8.2 for adjusting the

Q-factor value.

RPPG

Input

Received power packet gain (RPPG) calibration pin for foreign object detection (FOD)

tuning. Connect this pin to the center tap of a resistor divider to set the gain of the FOD.

The FOD is disabled by connecting the RPPG and RPPO pins to GND. Do not leave this

pin floating.

COMM2

Output

Open-drain output used to communicate with the transmitter. Connect a 47nF capacitor

from AC2 to COMM2.

RSV4

–

Reserved for internal use. Do not connect.

ALIGNY

Input

AC input for coil alignment guide. If not used, connect to GND through a 10kΩ resistor.

SDA

Input/Output

Serial data line. Open-drain pin. Connect a 5.1kΩ resistor to VDD18 pin.

ILIM

Input

Programmable over-current limit pin. Connect this pin to the center tap of a resistor

divider to set the current limit. For more information about the current limit function, see

section 8.5.

̅̅̅̅

Input

Active-LOW enable pin. Pulling this pin to logic HIGH forces the device into Shut Down

Mode. When connected to logic LOW, the device is enabled. Do not leave this pin

floating.

RSV5

–

Reserved for internal use. Do not connect.

C1, C6, J1, J2,

J3, J4, J5, J6

GND

Ground.

SINK

Output

Open-drain output for controlling the rectifier clamp. Connect a 36Ω resistor from this pin

to the VRECT pin.

INT

̅̅̅̅

Output

Interrupt flag pin. This is an open-drain output that signals fault interrupts. It is pulled LOW

if any of these faults exist: an over-voltage is detected, an over-current condition is

detected, the die temperature exceeds 140°C, or an external over-temperature condition

is detected on the TS/EOC pin. INT

̅̅̅̅ is also pulled LOW, if the device receives user data

from a P9242-R3.

It is also asserted LOW when EN is HIGH. Connect INT to VDD18 through a 10kΩ

resistor. See section 8.6 for additional conditions affecting the interrupt flag.

RPPO

Input

Received power packet offset (RPPO) calibration pin for FOD tuning. Connect this pin to

the center tap of the resistor divider to set the offset of the FOD. The FOD is disabled by

connecting the RPPG and RPPO pins to GND. Do not leave this pin floating.

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