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©2016 Integrated Device Technology, Inc.

Revision E, August 18, 2016

8413S12B Datasheet.

Table 7C. Jitter Specifications for Network Processor Core Clocks and High Speed PLLs, VDD = 3.3V ± 5%, VDDO_[A:E] =

3.3V ± 5%; and VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions. For additional information, refer to the Network Processor Core Clocks and High Speed

PLLs Application Note section in the datasheet.

NOTE 1: Total phase jitter after applying the evaluation bands to the system transfer function for Network Processor Clock Architecture and

High Speed PLLs. The transfer function is defined and illustrated in the Network Processor Core Clocks and High Speed PLLs Application

Note section in the datasheet.

NOTE 2: Measurement in the Frequency Domain. Evaluation Band with PLL mask applied: 10Hz - 40MHz.

NOTE 3: Jitter data is measured with Agilent E5052A Signal Source Analyzer.

Table 7D. AC Characteristics, VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_F = 3.3V ± 5%; and

VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

Symbol

Parameter

Test Conditions

Output

Minimum

Typical

Maximum

Units

JCORE_REFCLK

Total Jitter;

Peak-to-Peak

NOTE 1, 2, 3

ƒ = 50MHz, 25MHz Crystal Input,

Internal Processor PLL BW=1MHz

QF

32.8

70

ps

ƒ = 50MHz, 25MHz Crystal Input,

Internal Processor PLL BW=2MHz

QF

33

70.01

ps

ƒ = 50MHz, 25MHz Crystal Input,

Internal Processor PLL BW = 5MHz

QF

33.6

70.05

ps

ƒ = 50MHz, 25MHz Crystal Input,

Internal Processor PLL BW = 8MHz

QF

34.5

71.2

ps

ƒ = 50MHz, 25MHz Crystal Input,

Internal Processor PLL BW = 10MHz

QF

35.3

71.9

ps

JPLL_REFCLK

Total Jitter,

Peak-to-Peak

NOTE 1, 2, 3

ƒ = 125MHz, 25MHz Crystal Input,

High Speed PLL BW = 1MHz

QG

39.5

86.7

ps

ƒ = 125MHz, 25MHz Crystal Input,

High Speed PLL BW = 2MHz

QG

39.5

86.7

ps

ƒ = 125MHz, 25MHz Crystal Input,

High Speed PLL BW = 5MHz

QG

39.9

86.9

ps

ƒ = 125MHz, 25MHz Crystal Input,

High Speed PLL BW = 8MHz

QG

41.6

88.4

ps

ƒ = 125MHz, 25MHz Crystal Input,

High Speed PLL BW = 10MHz

QG

43.3

90

ps

Symbol

Parameter

Test Conditions

Output

Minimum

Typical

Maximum

Units

fOUT

Output Frequency

FSEL_[A:E] = 00

Q[A:E], nQ[A:E]

100

MHz

FSEL_[A:E] = 01

Q[A:E], nQ[A:E]

125

MHz

FSEL_[A:E] = 10

Q[A:E], nQ[A:E]

156.25

MHz

FSEL_[A:E] = 11

Q[A:E], nQ[A:E]

312.5

MHz

QF

50

MHz

QG

125

MHz

QREF[0:1]

25

MHz