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8413S12B Folha de dados(PDF) 8 Page - Renesas Technology Corp |
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8413S12B Folha de dados(HTML) 8 Page - Renesas Technology Corp |
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8 / 34 page ![]() 8 ©2016 Integrated Device Technology, Inc Revision E, August 18, 2016 8413S12B Datasheet. Table 6. Input Frequency Characteristics, VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_F = 3.3V ± 5%; or VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C AC Electrical Characteristics Table 7A. PCI Express Jitter Specifications, VDD = 3.3V ± 5%, VDDO_[A:E] = 3.3V ± 5%; and VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. NOTE 4: This parameter is guaranteed by characterization. Not tested in production. Table 7B. Serial Rapid IO Switch Jitter Specification, VDD = 3.3V ± 5%, VDDO_[A:E] = 3.3V ± 5%; and VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. For additional information, refer to the Serial Rapid IO Application Note section in the datasheet. NOTE 1: Total phase jitter after applying the evaluation bands to the system transfer function for the IDT sRIO Tsi57x and Tsi620 Product Families. The transfer function is defined and illustrated in the Serial Rapid IO Application Note section in the datasheet and the IDT hardware manual of the Tsi57x and Tsi620. Total RMS phase jitter allowed on the reference clock of the Tsi57x and Tsi620 is specified at 3ps (max). NOTE 2: Evaluation band with sRIO mask applied: 10Hz - 40MHz. NOTE 3: Total phase jitter includes random and deterministic jitter. NOTE 4: Jitter data is measured with Agilent E5052A Signal Source Analyzer. Symbol Parameter Test Conditions Minimum Typical Maximum Units FIN Input Frequency CLK, nCLK 25 MHz XTAL_IN, XTAL_OUT 25 MHz Symbol Parameter Test Conditions Minimum Typical Maximum PCIe Industry Specification Units tj (PCIe Gen 1) Phase Jitter Peak-to-Peak; NOTE 1, 4 ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 14.27 24.35 86 ps tREFCLK_HF_R MS (PCIe Gen 2) Phase Jitter RMS; NOTE 2, 4 ƒ = 100MHz, 25MHz Crystal Input High Band: 1.5MHz - Nyquist (clock frequency/2) 1.47 3.04 3.10 ps tREFCLK_LF_R MS (PCIe Gen 2) Phase Jitter RMS; NOTE 2, 4 ƒ = 100MHz, 25MHz Crystal Input Low Band: 10kHz - 1.5MHz 0.17 0.67 3.0 ps tREFCLK_RMS (PCIe Gen 3) Phase Jitter RMS; NOTE 3, 4 ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.37 0.79 0.8 ps Symbol Parameter Test Conditions Minimum Typical Maximum IDT sRIO Specification Units JCLK_REF Total Phase Jitter, RMS; NOTE 1, 2, 3, 4 ƒ = 125MHz, 25MHz Crystal Input, HCSL Output Clocks 0.64 1.55 3 ps |
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