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8413S12B Folha de dados(PDF) 3 Page - Renesas Technology Corp

Nome de Peças 8413S12B
Descrição Electrónicos  HCSL/ LVCMOS Clock Generator
PDF  34 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

8413S12B Folha de dados(HTML) 3 Page - Renesas Technology Corp

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©2016 Integrated Device Technology, Inc.
Revision E, August 18, 2016
8413S12B Datasheet.
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 18, 38
GND
Power
Power supply ground.
2,
3
FSEL_A0.
FSEL_A1
Input
Pulldown
Selects the QAx, nQAx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
4,
5
FSEL_B0,
FSEL_B1
Input
Pulldown
Selects the QBx, nQBx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
6,
7
FSEL_C0,
FSEL_C1
Input
Pulldown
Selects the QCx, nQCx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
8,
9
FSEL_D0,
FSEL_D1
Input
Pulldown
Selects the QDx, nQDx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
10,
12
FSEL_E0,
FSEL_E1
Input
Pulldown
Selects the QEx, nQEx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
11
VDDA
Power
Analog supply pin.
13, 16, 19,
36, 37, 54,
55, 72
nc
Unused
No connect.
14,
15
XTAL_IN,
XTAL_OUT
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
17
REF_SEL
Input
Pullup
Input source control pin. See Table 3C. LVCMOS/LVTTL interface levels.
20, 39, 53
VDD
Power
Core supply pins.
21
PLL_SEL
Input
Pullup
PLL bypass control pin. See Table 3B. LVCMOS/LVTTL interface levels.
22
CLK
Input
Pulldown
Non-inverting differential clock input.
23
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to VDD/2.
24
OE_A
Input
Pullup
Active HIGH output enable for Bank A outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
25
VDDO_A
Power
Bank A (HCSL) output supply pin. 3.3 V supply.
26, 27
QA0, nQA0
Output
Differential output pairs. HCSL interface levels.
28, 29
QA1, nQA1
Output
Differential output pairs. HCSL interface levels.
30
OE_B
Input
Pullup
Active HIGH output enable for Bank B outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
31, 32
QB0, nQB0
Output
Differential output pair. HCSL interface levels.
33, 34
QB1, nQB1
Output
Differential output pair. HCSL interface levels.
35
VDDO_B
Power
Bank B (HCSL) output supply pin. 3.3V supply.
40
OE_C
Input
Pullup
Active HIGH output enable for Bank C outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
41, 42
QC0, nQC0
Output
Differential output pair. HCSL interface levels.
43, 44
QC1, nQC1
Output
Differential output pair. HCSL interface levels.
45
VDDO_C
Power
Bank C (HCSL) output supply pin. 3.3V supply.
46
VDDO_D
Power
Bank D (HCSL) output and HCSL reference circuit supply pin. Must be
connected to 3.3V to use any of the HCSL outputs.
47, 48
QD0, nQD0
Output
Differential output pair. HCSL interface levels.
49, 50
QD1, nQD1
Output
Differential output pair. HCSL interface levels.



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