IC42S16100 datasheet(28/78 Pages) ICSI

Nome de Peças	IC42S16100

Descrição Electrónicos	512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

PDF	78 Pages

Scroll/Zoom	100%

Fabricante Electrônico	ICSI [Integrated Circuit Solution Inc]

Página de início	http://www.icsi.com.tw

Logo

28 / 78 page

IC42S16100

Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

Interval Between Write and Read Commands

A new read command can be executed while a write cycle

is in progress, i.e., before that cycle completes. Data

corresponding to the new read command is output after

the CAS latency has elapsed from the point the new read

command was executed. The I/On pins must be placed in

the HIGH impedance state at least one cycle before data

is output during this operation.

The interval (tCCD) between command must be at least one

clock cycle.

The selected bank must be set to the active state before

executing this command.

I/O

WRITE A0

READ B0

COMMAND

CLK

DIN A0

DOUT B0

DOUT B2

DOUT B1

DOUT B3

tCCD

HI-Z

WRITE (CA=A, BANK 0)

READ (CA=B, BANK 0)

I/O

WRITE A0

READ B0

COMMAND

CLK

DIN A0

DOUT B0

DOUT B2

DOUT B1

DOUT B3

tCCD

HI-Z

WRITE (CA=A, BANK 0)

READ (CA=B, BANK 0)

CAS latency = 2, burst length = 4

CAS latency = 3, burst length = 4

Don’t Care

IC42S16100 Folha de dados(PDF) 28 Page - Integrated Circuit Solution Inc

IC42S16100 Folha de dados(HTML) 28 Page - Integrated Circuit Solution Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Folha de dados Download

Ligação URL