VSC8540RT datasheet(45/87 Pages) MICROCHIP

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DS60001603E-page 45

VSC8540RT

Note:

When bits 5:4 are set to jumbo packet mode, the default maximum packet values are based on 100 ppm

driven reference clock to the device. Controlling the ppm offset between the MAC and the PHY as specified

in the bit description results in a higher jumbo packet length.

6.2.19

INTERRUPT MASK

These bits control the device interrupt mask. The following table shows the settings available.

Note:

When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this pin reflects the state of

bit 26.15. Clearing this bit only inhibits the MDINT pin from being asserted. Also, before enabling this bit,

read register 26 to clear any previously inactive interrupts pending that will cause bit 25.15 to be set.

PICMG 2.16 reduced power mode R/W

Sticky bit.

1: Enabled.

11:6

Reserved

Reserved.

5:4

Jumbo packet mode

R/W

Sticky bit.

00: Normal IEEE 1.5 kB packet length.

01: 9 kB jumbo packet length (12 kB with

60 ppm or better reference clock).

10: 12 kB jumbo packet length (16 kB with

70 ppm or better reference clock).

11: Reserved.

3:1

Reserved

Reserved.

Connector loopback

R/W

1: Enabled.

TABLE 6-22:

INTERRUPT MASK, ADDRESS 25 (0X19)

Bit

Name

Access

Description

Default

MDINT interrupt status enable

R/W

Sticky bit. 1: Enabled.

Speed state change mask

R/W

Sticky bit. 1: Enabled.

Link state change mask

R/W

Sticky bit. 1: Enabled.

FDX state change mask

R/W

Sticky bit. 1: Enabled.

Autonegotiation error mask

R/W

Sticky bit. 1: Enabled.

Autonegotiation complete mask

R/W

Sticky bit. 1: Enabled.

Inline-powered device (PoE) detect mask R/W

Sticky bit. 1: Enabled.

Symbol error interrupt mask

R/W

Sticky bit. 1: Enabled.

Fast link failure interrupt mask

R/W

Sticky bit. 1: Enabled.

Wake-on-LAN event interrupt mask

R/W

Sticky bit. 1: Enabled.

Extended interrupt mask

R/W

Sticky bit. 1: Enabled.

Reserved

Reserved.

False carrier interrupt mask

R/W

Sticky bit. 1: Enabled.

Reserved

Reserved.

Reserved

Reserved.

RX_ER interrupt mask

R/W

Sticky bit. 1: Enabled.

TABLE 6-21:

EXTENDED PHY CONTROL 2, ADDRESS 24 (0X18) (CONTINUED)

Bit

Name

Access

Description

Default

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