ADP2442ACPZ-R7 datasheet(21/36 Pages) AD

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Data Sheet

ADP2442

Rev. B | Page 21 of 36

Table 8. Inductor Values for Various VIN, VOUT, and fSW

Combinations

Inductor Values

fSW (kHz)

VIN (V)

VOUT (V)

Min (μH)

Max (μH)

300

3.3

300

3.3

300

3.3

300

600

3.3

600

3.3

600

3.3

600

1000

6.8

1000

To avoid inductor saturation and ensure proper operation, choose

the inductor value so that neither the saturation current nor the

maximum temperature rated current ratings are exceeded.

Inductor manufacturers specify both of these ratings in data

sheets, or the rating can be calculated as follows:

)

(

MAX

LOAD

PEAK







(10)

where:

ILOAD (MAX) is the maximum dc load current.

ΔIL is the peak-to-peak inductor ripple current.

IL_PEAK is the peak inductor current.

Table 9. Recommended Inductors

Value (μH)

Small Inductors

(<10 mm × 10 mm)

Large Inductors

(>10 mm × 10 mm)

XAL4040-103ME

MSS1260

LPS6235-183ML

MSS1260

LPS6235-33ML

MSS1260

XAL4040-153ME

MSS1260

Output Capacitor Selection

The output capacitor selection affects both the output voltage

ripple and the loop dynamics of the regulator. The ADP2442 is

designed to operate with small ceramic output capacitors that

have low ESR and ESL; therefore, the device easily meets tight

output voltage ripple specifications. For best performance, use

X5R or X7R dielectric capacitors with a voltage rating that is

1.5 times the output voltage and avoid using Y5V and Z5U

dielectric capacitors, which have poor temperature and dc bias

characteristics. Table 10 lists recommended capacitors from

Murata and Taiyo Yuden.

Table 10. Recommended Output Capacitors

Vendor

Capacitor

Murata

Taiyo Yuden

10 μF/25 V

GRM32DR71E106KA12L

TMK325B7106KN-TR

22 μF/25 V

GRM32ER71E226KE15L

TMK325B7226MM-TR

47 μF/6.3 V

GCM32ER70J476KE19L

JMK325B7476MM-TR

4.7 μF/50 V

GRM31CR71H475KA12L

UMK325B7475MMT

For acceptable maximum output voltage ripple, determine the

minimum output capacitance, COUT (MIN), as follows:

























)

(

MIN

OUT

RIPPLE

ESR

(11)

Therefore,

)

(

)

(

ESR

RIPPLE

MIN

OUT















(12)

where:

ΔVRIPPLE is the allowable peak-to-peak output voltage ripple.

ΔIL is the inductor ripple current.

ESR is the equivalent series resistance of the capacitor.

fSW is the switching frequency of the regulator.

When there is a step load requirement, choose the output

capacitor value based on the value of the step load. Use the

following equation to determine the maximum acceptable

output voltage droop/overshoot caused by the step load:





















DROOP

STEP

OUT

MIN

OUT

)

(

)

(

(13)

where:

ΔIOUT (STEP) is the load step.

fSW is the switching frequency of the regulator.

ΔVDROOP is the maximum allowable output voltage droop/overshoot.

Select the larger of the output capacitances derived from

Equation 12 and Equation 13. When choosing the type of ceramic

capacitor for the output filter of the regulator, select a capacitor

with a nominal capacitance that is 20% to 30% larger than the

calculated value because the effective capacitance degrades with dc

voltage and temperature. Figure 60 shows the capacitance loss

resulting from the dc bias voltage for two capacitors (X7R MLCC

capacitors from Murata are shown in Figure 60).

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