ADP2442ACPZ-R7 datasheet(25/36 Pages) AD

25 / 36 page

Data Sheet

ADP2442

Rev. B | Page 25 of 36

In this example, the values listed in Table 12 are substituted for

the variables in Equation 12 and Equation 13.

Table 12. Requirements

Parameter

Test Conditions/Comments

Value

Ripple Current

Fixed at 0.3 A for the ADP2442

0.3 A

Voltage Ripple

1% of VOUT

50 mV

Voltage Droop Due

to Load Transient

2% of VOUT

100 mV

ESR

5 mΩ

fSW

700 kHz

The calculation based on the output voltage ripple (see

Equation 12) dictates that the minimum output capacitance is

μF

)

mΩ

(

kHz

700

)

(











MIN

OUT

Whereas the calculation based on the transient load (see

Equation 13) dictates that the minimum output capacitance is

kHz

700

)

(









MIN

OUT

To meet both requirements, use the value determined by the

latter equation. As shown in Figure 60, capacitance degrades

with dc bias; therefore, choose a capacitor that is 1.5 times the

calculated value.

COUT = 1.5 × 22 μF = 32 μF

Compensation Selection

Calculate the compensation component values for the feedback

loop using the following equations:

REF

OUT

CROSSOVER

COMP









COMP

ZERO

COMP









Selecting the crossover frequency to be 1/12 of the switching

frequency and placing the zero frequency at 1/8 of the crossover

frequency ensures that there is adequate phase margin in

the system.

Table 13. Calculated Parameter Value

Parameter

Test Conditions/Comments

Value

fCROSSOVER

1/12 of fSW

58.3 kHz

fZERO

1/8 of fCROSSOVER

7.3 kHz

VREF

Fixed reference

0.6 V

Transconductance of error

amplifier

250 μA/V

GCS

Current sense gain

2 A/V

COUT

Output capacitor

22 μF

VOUT

Output voltage

5 V

Based on the values listed in Table 13, calculate the compen-

sation value:

kΩ

121

250









COMP

The closest standard resistor value is 118 kΩ. Therefore,

180

185

118











COMP

SYSTEM CONFIGURATION

Configure the system as follows; though the steps are not

sequential, they all must be completed:



Connect a capacitor of 1 μF between the VCC and PGND

pins and another capacitor of 1 μF between the VCC and

AGND pins. For best performance, use ceramic X5R or

X7R capacitors with a 25 V voltage rating.



Connect a ceramic capacitor of 10 nF with a 50 V voltage

rating between the BST and SW pins.



Connect a resistor between the FREQ and AGND pins as

close as possible to the IC.



If using the power-good feature, connect a 50 kΩ pull-up

resistor to a 5 V external supply.



For synchronization, connect an external clock with a

frequency of 700 kHz to the SYNC/MODE pin. Connect

the external clock to AGND to activate pulse skip mode or

connect it to VCC for forced fixed frequency mode.

See Figure 63 for a schematic of this design example and Table 14

for the calculated component values.

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