USB2640 datasheet(41/60 Pages) MICROCHIP

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DS00001947C-page 41

USB2640/USB2641

7.3.6

I2C EEPROM

The I2C EEPROM interface implements a subset of the I2C Master Specification (Please refer to the Philips Semicon-

ductor Standard I2C-Bus Specification for details on I2C bus protocols). The device’s I2C EEPROM interface is designed

to attach to a single “dedicated” I2C EEPROM, and it conforms to the Standard-mode I2C Specification (100 kbps trans-

fer rate and 7-bit addressing) for protocol and electrical compatibility.

The device acts as the master and generates the serial clock SCL, controls the bus access (determines which device

acts as the transmitter and which device acts as the receiver), and generates the START and STOP conditions.

7.3.6.1

Implementation Characteristics

The device will only access an EEPROM using the sequential read protocol.

7.3.6.2

Pull-Up Resistor

The circuit board designer is required to place external pull-up resistors (10 k

 recommended) on the SDA/SMBDATA

& SCL/SMBCLK/CFG_SEL0 lines (per SMBus 1.0 Specification, and EEPROM manufacturer guidelines) to VDD33 in

order to assure proper operation.

7.3.7

IN-CIRCUIT EEPROM PROGRAMMING

The EEPROM can be programmed via automatic testing test equipment (ATE) by pulling nRESET low which tri-states

the device’s EEPROM interface and allows an external source to program the EEPROM.

7.4

Default Configuration Option:

The Microchip device can be configured via its internal default configuration. Please see Section 7.3.2, "EEPROM Data

Descriptor" for specific details on how to enable default configuration. Please refer to Table 7-1 for the internal default

values that are loaded when this option is selected.

7.5

Reset

There are two different resets that the device experiences. One is a hardware reset (either from the internal POR reset

circuit or via the nRESET pin) and the second is a USB Bus Reset.

7.5.1

INTERNAL POR HARDWARE RESET

All reset timing parameters are ensured by design.

7.5.2

EXTERNAL HARDWARE NRESET

A valid hardware reset is defined as assertion of nRESET for a minimum of 1

s after all power supplies are within oper-

ating range. While reset is asserted, the device (and its associated external circuitry) consumes less than 500

A of

current from the upstream USB power source.

Assertion of nRESET (external pin) causes the following:

All downstream ports are disabled, and PRTCTL power to downstream devices is removed.

The PHYs are disabled, and the differential pairs will be in a high-impedance state.

All transactions immediately terminate; no states are saved.

All internal registers return to the default state (in most cases, 00h).

The external crystal oscillator is halted.

The PLL is halted.

Note:

Extensions to the I2C Specification are not supported.

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