Si5350B

14

Rev. 0.9

4.3.4. Power Down (PDN)

An optional power down control pin allows a full shutdown of the Si5350B to minimize power consumption when its

output clocks are not being used. The Si5350B is in normal operation when the PDN pin is held low and is in power

down mode when held high. Power consumption when the device is in power down mode is indicated in Table 2 on

page 4.

4.4. Voltage Control Input (VC)

The VCXO architecture of the Si5350B eliminates the need for an external pullable crystal. Only a standard, low-

cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.

The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the

VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and

reliable startup and operation. Refer to Table 3 on page 5 for VCXO specification details.

A unique feature of the Si5350B is its ability to generate multiple output frequencies controlled by the same control

voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same

reference. An example is illustrated in Figure 10.

Figure 10. Generating One Or More Synchronous Clocks

4.4.1. Control Voltage Gain (kV)

The voltage level on the VC pin directly controls the output frequency. The rate of change in output clock frequency

(kv) is configurable from 18 ppm/V up to 150 ppm/V. This allows a configurable pull range from ±30 ppm to

A key advantage of the VCXO design in the Si5350B is its highly linear tuning range. This allows better control of

PLL stability and jitter performance over the entire control voltage range.

CLK0

VC

Multi

Synth

2

CLK1

CLK2

Additional MultiSynths can be

added to generate multiple

synchronous clocks with

different output frequencies

XA

XB

OSC

VCXO

Multi

Synth

0

Multi

Synth

1

Control

Voltage

Fixed Frequency

Crystal (non-pullable)