Si5350B

10

Rev. 0.9

3. Functional Description

divider on each output. A block diagram of both the 3-output and the 8-output clock generators are shown in

Figure 4. Free-running clocks are generated from the on-chip oscillator + PLL, and a separate voltage controlled

oscillator (VCXO) is used to generate synchronous clocks. A fixed-frequency non-pullable standard AT-cut crystal

provides frequency stability for both the internal oscillator and VCXO. The flexible synthesis architecture of the

Si5350B generates up to eight non-integer related frequencies and any combination of free-running and/or

synchronous clocks.

Figure 4. Block Diagram of the 3 and 8 Output Si5350B Devices

10-MSOP

MultiSynth 3

F1_2

F2_2

R2

FS

MultiSynth 2

VDD

GND

CLK2

F1_0

F2_0

R0

FS

MultiSynth 0

F1_1

F2_1

R1

FS

MultiSynth 1

CLK0

CLK1

VDDO

F1_3

F2_3

R3

FS

MultiSynth 3

F1_2

F2_2

R2

FS

MultiSynth 2

20-QFN, 24-QSOP

VDD

GND

CLK2

CLK3

VDDOB

Control

Logic

P2

P3

P0

P1

F1_0

F2_0

R0

FS

MultiSynth 0

F1_1

F2_1

R1

FS

MultiSynth 1

CLK0

CLK1

VDDOA

R6

R7

CLK6

CLK7

VDDOD

F1_4

F2_4

R4

FS

MultiSynth 4

F1_5

F2_5

R5

FS

MultiSynth 5

CLK4

CLK5

VDDOC

F1_6

MultiSynth 6

F1_7

MultiSynth 7

Control

Logic

P0

PLL

OSC

XA

XB

VC

OSC

XA

XB

VC

PLL

VCXO

VCXO