LOAD

V Supply

load

Current

+

VOUT

Vcc

R1

R3

+

Vshunt

R4

+

Vcc

R2

Vcc

LPV821

R5

R6

Vbias

LPV821

To ADC REF

input

13

LPV821

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SNOSD36 – AUGUST 2017

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Typical Applications (continued)

Figure 25. Low-Side Current Measurement

9.2.1.1 Design Requirements

The design requirements are as follows:

•

Supply Voltage: 3.3 V DC

•

Input: 1 A (Max)

•

Output: 1.65V ± 1.54 V ; (110 mV to 3.19 V)

9.2.1.2 Detailed Design Procedure

Referring to Figure 25, the load current passing though the shunt resistor (Rshunt) develops the shunt voltage,

Vshunt across the resistor. The shunt voltage is then amplified by the LPV821 by the ratio of R4 by R3 . The gain

of the difference amplifier is set by the ratio of R4 to R3 . To minimize errors, set R2 = R4 and R1 = R3 . The

bias voltage is supplied by buffering a resistor divider using a second LPV821 nanopower op amp. The circuit

equations are provided below.

(1)

(2)

(3)

(4)

(5)

(6)

The tolerance of the shunt resistor, the ratio of R4 to R3 and the ratio of R2 to R1 are the main sources of gain

error in the signal path. To optimize the cost, a shut resistor with a tolerance of 0.5% was chosen. The main

sources of offset errors in the circuit are the voltage divider network comprise of R5, R6 and how closely the ratio

of R4 / R3 matches the ration of R2 / R1. The latter value affects the CMRR of the difference amplifier, ultimately

translating to an offset error.

The shunt voltage is scaled down by a divider network made of R1 and R2 before reaching the LPV821 amplifier

stage. The voltage present at the non-inverting node of the LPV821 should not exceed the common-mode range

of the device. The extremely low offset voltage and drift of the LPV821 ensures minimized offset error in the

measurement.