LQFP176 datasheet(17/133 Pages) STMICROELECTRONICS

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DocID15131 Rev 9

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SPC560B54x/6x

Package pinouts and signal descriptions

132

3.3

Pad configuration during standby mode exit

Pad configuration (input buffer enable, pull enable) for low-power wakeup pads is controlled

by both the SIUL and WKPU modules. During standby exit, all low power pads

PA[0,1,2,4,15], PB[1,3,8,9,10](a), PC[7,9,11], PD[0,1], PE[0,9,11], PF[9,11,13](b),

PG[3,5,7,9](b), PI[1,3](c) are configured according to their respective configuration done in

the WKPU module. All other pads will have the same configuration as expected after a

reset.

The TDO pad has been moved into the STANDBY domain in order to allow low-power

debug handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad

while in STANDBY mode. At this time the pad is configured as an input. When no debugger

is connected the TDO pad is floating causing additional current consumption.

To avoid the extra consumption TDO must be connected. An external pull-up resistor in the

range of 47–100 kOhms should be added between the TDO pin and VDD. Only if the TDO

pin is used as an application pin and a pull-up cannot be used should a pull-down resistor

with the same value be used instead between the TDO pin and GND.

3.4

Voltage supply pins

Voltage supply pins are used to provide power to the device. Three dedicated

VDD_LV/VSS_LV supply pairs are used for 1.2 V regulator stabilization.

PB[8, 9] ports have wakeup functionality in all modes except STANDBY.

PF[9,11,13], PG[3,5,7,9], PI[1,3] are not available in the 100-pin LQFP.

PI[1,3] are not available in the 144-pin LQFP.

Table 4. Voltage supply pin descriptions

Port pin

Function

Pin number

LQFP100

LQFP144

LQFP176

LBGA208

VDD_HV

Digital supply voltage

15, 37, 70, 84

19, 51, 100,

123

6, 27, 59, 85,

124, 151

C2, D9, E16,

G13, H3, N4,

N9, R5

VSS_HV

Digital ground

14, 16, 35,

69, 83

18, 20, 49,

99, 122

7, 26, 28, 57,

86, 123, 150

G7, G8, G9,

G10, H7, H8,

H9, H10, J7,

J8, J9, J10,

K7, K8, K9,

K10

VDD_LV

1.2 V decoupling pins. Decoupling

capacitor must be connected

between these pins and the

nearest VSS_LV pin.

(1)

19, 32, 85

23, 46, 124

31, 54, 152

D8, K4, P7

VSS_LV

1.2 V decoupling pins. Decoupling

capacitor must be connected

between these pins and the

nearest VDD_LV pin.

(1)

18, 33, 86

22, 47, 125

30, 55, 153

C8, J2, N7

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