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EM357-RTR Folha de dados(PDF) 144 Page - Silicon Laboratories

Nome de Peças EM357-RTR
Descrição Electrónicos  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  241 Pages
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Fabricante Electrônico  SILABS [Silicon Laboratories]
Página de início  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EM357-RTR Folha de dados(HTML) 144 Page - Silicon Laboratories

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9.4. Interrupts
Each timer has its own top-level NVIC interrupt. Writing 1 to the INT_TIMx bit in the INT_CFGSET register enables
the TIMx interrupt, and writing 1 to the INT_TIMx bit in the INT_CFGCLR register disables it. "11. Interrupt System"
on page 190 describes the interrupt system in detail.
Several kinds of timer events can generate a timer interrupt, and each has a status flag in the INT_TIMxFLAG
register to identify the reason(s) for the interrupt:

INT_TIMTIF – set by a rising edge on an external trigger, either edge in gated mode

INT_TIMCCRyIF – set by a channel y input capture or output compare event

INT_TIMUIF – set by a UEV
Clear bits in INT_TIMxFLAG by writing a 1 to their bit position. When a channel is in capture mode, reading the
TIMx_CCRy register will also clear the INT_TIMCCRyIF bit.
The INT_TIMxCFG register controls whether or not the INT_TIMxFLAG bits actually request a top-level NVIC timer
interrupt. Only the events whose bits are set to 1 in INT_TIMxCFG can do so.
If an input capture or output compare event occurs and its INT_TIMMISSCCyIF is already set, the corresponding
capture/compare missed flag is set in the INT_TMRxMISS register. Clear a bit in the INT_TMRxMISS register by
writing a 1 to it.



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