EM357-RTR datasheet(124/241 Pages) SILABS

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Rev 1.3

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9.3.3.3. External Clock Source Mode 2

This mode is selected by writing TIM_ECE = 1 in the TIMx_SMCR register. The counter can count at each rising or

falling edge on the external trigger input ETR.

The TIM_EXTRIGSEL bits in the TIMx_OR register select a clock signal that drives ETR, as shown in Table 9.2.

Figure 9.15 gives an overview of the external trigger input block.

Figure 9.15. External Trigger Input Block

For example, to configure the up-counter to count each 2 rising edges on ETR, use the following procedure:



Since no filter is needed in this example, write TIM_ETF = 0000 in the TIMx_SMCR register.



Set the prescaler: Write TIM_ETPS = 01 in the TIMx_SMCR register.



Select rising edge detection on ETR: WriteTIM_ETP = 0 in the TIMx_SMCR register.



Enable external clock mode 2: Write TIM_ECE = 1 in the TIMx_SMCR register.



Enable the counter: Write TIM_CEN = 1 in the TIMx_CR1 register.

The counter counts once each two ETR rising edges. The delay between the rising edge on ETR and the actual

clock of the counter is due to the resynchronization circuit on the ETRP signal.

Figure 9.16 illustrates counting every two rising edges of ETR using external clock mode 2.

Table 9.2. TIM_EXTRIGSEL Clock Signal Selection

TIM_EXTRIGSEL Bits

Clock Signal Selection

PCLK (peripheral clock). When running from the 24 MHz crystal oscillator, the PCLK

frequency is 12 MHz. When the 12 MHz RC oscillator is in use, the frequency is

6 MHz.

Calibrated 1 kHz internal RC oscillator

Optional 32.786 kHz clock

TIMxCLK pin. If the TIM_CLKMSKEN bit in the TIMx_OR register is set, this signal is

AND’ed with the TIMxMSK pin providing a gated clock input.

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