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EM357-RTR Folha de dados(PDF) 122 Page - Silicon Laboratories

Nome de Peças EM357-RTR
Descrição Electrónicos  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  241 Pages
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Fabricante Electrônico  SILABS [Silicon Laboratories]
Página de início  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EM357-RTR Folha de dados(HTML) 122 Page - Silicon Laboratories

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Rev 1.3
122
Figure 9.11. Counter Timing Diagram, Update Event with TIM_ARBE = 1 (Counter Overflow)
9.3.3. Clock Selection
The counter clock can be provided by the following clock sources:

Internal clock (PCLK)

External clock mode 1: external input pin (TIy)

External clock mode 2: external trigger input (ETR)

Internal trigger input (ITR0): using the other timer as prescaler. Refer to "9.3.14.1. Using One Timer as
Prescaler for the Other Timer" on page 139 for more details.
9.3.3.1. Internal Clock Source (CK_INT)
The internal clock is selected when the slave mode controller is disabled (TIM_SMS = 000 in the TIMx_SMCR
register). In this mode, the TIM_CEN, TIM_DIR (in the TIMx_CR1 register), and TIM_UG bits (in the TIMx_EGR
register) are actual control bits and can be changed only by software, except for TIM_UG, which remains cleared
automatically. As soon as the TIM_CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 9.12 shows the behavior of the control circuit and the up-counter in normal mode, without prescaling.
Figure 9.12. Control Circuit in Normal Mode, Internal Clock Divided by 1



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