PIC18F8720 datasheet(71/380 Pages) MICROCHIP

71 / 380 page

 2004 Microchip Technology Inc.

DS39609B-page 69

PIC18F6520/8520/6620/8620/6720/8720

EXAMPLE 5-3:

WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

5.5.2

WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

5.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. The WRERR bit is set when a

write operation is interrupted by a MCLR Reset, or a

WDT Time-out Reset during normal operation. In these

situations, users can check the WRERR bit and rewrite

the location.

5.5.4

PROTECTION AGAINST

SPURIOUS WRITES

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 23.0 “Special Features of the

CPU” for more detail.

5.6

Flash Program Operation During

Code Protection

See Section 23.0 “Special Features of the CPU” for

details on code protection of Flash program memory.

TABLE 5-2:

REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

PROGRAM_MEMORY

BSF

EECON1, EEPGD

; point to Flash program memory

BCF

EECON1, CFGS

; access Flash program memory

BSF

EECON1, WREN

; enable write to memory

BCF

INTCON, GIE

; disable interrupts

MOVLW

55h

MOVWF

EECON2

; write 55H

Required

MOVLW

AAh

Sequence

MOVWF

EECON2

; write AAH

BSF

EECON1, WR

; start program (CPU stall)

NOP

BSF

INTCON, GIE

; re-enable interrupts

DECFSZ

COUNTER_HI

; loop until done

BRA

PROGRAM_LOOP

BCF

EECON1, WREN

; disable write to memory

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

TBLPTRU

—

bit 21

Program Memory Table Pointer Upper Byte

(TBLPTR<20:16>)

--00 0000

TBPLTRH

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

0000 0000

TBLPTRL

Program Memory Table Pointer High Byte (TBLPTR<7:0>)

0000 0000

TABLAT

Program Memory Table Latch

0000 0000

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 0000

EECON2

EEPROM Control Register 2 (not a physical register)

—

EECON1

EEPGD

CFGS

—

FREE

WRERR

WREN

xx-0 x000

uu-0 u000

IPR2

—

CMIP

—EEIP

BCLIP

LVDIP

TMR3IP

CCP2IP

---1 1111

PIR2

—

CMIF

—EEIF

BCLIF

LVDIF

TMR3IF

CCP2IF

---0 0000

PIE2

—

CMIE

—EEIE

BCLIE

LVDIE

TMR3IE

CCP2IE

---0 0000

Legend:

= unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.

Shaded cells are not used during Flash/EEPROM access.

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