PIC18F8720 datasheet(44/380 Pages) MICROCHIP

44 / 380 page

PIC18F6520/8520/6620/8620/6720/8720

DS39609B-page 42

 2004 Microchip Technology Inc.

4.2

Return Address Stack

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC

(Program Counter) is pushed onto the stack when a

CALL

or RCALL instruction is executed, or an interrupt

is Acknowledged. The PC value is pulled off the stack

on a RETURN, RETLW or a RETFIE instruction. PCLATU

and PCLATH are not affected by any of the RETURN or

CALL

instructions.

The stack operates as a 31-word by 21-bit RAM and a

5-bit stack pointer, with the stack pointer initialized to

00000b after all Resets. There is no RAM associated

with stack pointer 00000b. This is only a Reset value.

During a CALL type instruction, causing a push onto the

stack, the stack pointer is first incremented and the

RAM location pointed to by the stack pointer is written

with the contents of the PC. During a RETURN type

instruction, causing a pop from the stack, the contents

of the RAM location pointed to by the STKPTR are

transferred to the PC and then the stack pointer is

decremented.

The stack space is not part of either program or data

space. The stack pointer is readable and writable and

the address on the top of the stack is readable and writ-

able through SFR registers. Data can also be pushed

to, or popped from the stack using the top-of-stack

SFRs. Status bits indicate if the stack pointer is at, or

beyond the 31 levels provided.

4.2.1

TOP-OF-STACK ACCESS

The top of the stack is readable and writable. Three

contents of the stack location pointed to by the

STKPTR register. This allows users to implement a

software stack if necessary. After a CALL, RCALL or

interrupt, the software can read the pushed value by

reading the TOSU, TOSH and TOSL registers. These

values can be placed on a user defined software stack.

At return time, the software can replace the TOSU,

TOSH and TOSL and do a return.

The user must disable the global interrupt enable bits

during

this

time

prevent

inadvertent

stack

operations.

4.2.2

RETURN STACK POINTER

(STKPTR)

The STKPTR register contains the stack pointer value,

the STKFUL (Stack Full) status bit and the STKUNF

(Stack Underflow) status bits. Register 4-2 shows the

STKPTR register. The value of the stack pointer can be

0 through 31. The stack pointer increments when val-

ues are pushed onto the stack and decrements when

values are popped off the stack. At Reset, the stack

pointer value will be ‘0’. The user may read and write

the stack pointer value. This feature can be used by a

Real-Time

Operating

System

for

return

stack

maintenance.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit can only be cleared in software or

by a POR.

The action that takes place when the stack becomes

full, depends on the state of the STVREN (Stack Over-

flow

Reset

Enable)

configuration

bit.

Refer

Section 24.0 “Instruction Set Summary” for a

description of the device configuration bits. If STVREN

is set (default), the 31st push will push the (PC + 2)

value onto the stack, set the STKFUL bit and reset the

device. The STKFUL bit will remain set and the stack

pointer will be set to ‘0’.

If STVREN is cleared, the STKFUL bit will be set on the

31st push and the stack pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and STKPTR will remain at 31.

When the stack has been popped enough times to

unload the stack, the next pop will return a value of zero

to the PC and sets the STKUNF bit, while the stack

pointer remains at ‘0’. The STKUNF bit will remain set

until cleared in software or a POR occurs.

Note:

Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the Reset vector, where the

stack conditions can be verified and

appropriate actions can be taken.

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