PIFE32251B-R68MS datasheet(40/157 Pages) TI1

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TPS650830

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Specifications

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Maximum load regulation with

respect to nominal Vout

ULQ/Auto Mode, VVIN = 7.4 V, IOUT = 0 A

to IMAX, Measured at the regulation point

output capacitor with Kelvin connections

made directly from the regulation point to

the differential feedback pins (FBVR5P -

FBVR5N).

-0.5%

0.75%

Maximum total output voltage load

transient variation with respect to

nominal Vout

DC and AC, ULQ/Auto Mode, VVIN = 5.7

V to 21 V (when Vout = 5 V), VVIN = 5.4 V

to 21 V (when Vout = 1.8 V), IOUT = 0 A to

70% max load, 70% max load to 0 mA

and IOUT = 30% max load to max load,

max load to 30% max load, di/dt = 2.5

A/µs, Measured at the regulation point

output capacitor with Kelvin connections

made directly from the regulation point to

the differential feedback pins (FBVR5P -

FBVR5N).

-5%

VR5_Controller switching

frequency

PWM Mode (NVDC# = 3.3 V)

(TPS650830, TPS650832)

875

925

kHz

VR5_Controller switching

frequency

PWM Mode (NVDC# = 3.3 V =

programmed to low switching frequency)

430

500

550

kHz

PWM Mode (NVDC# = GND =

programmed to high switching frequency)

Frequency drops at Vin < 6 V close to

Vout = 5 V to extend Ton.

875

925

Soft-Start total turn-on time (start-

up time + output ramp-up time)

Time to start switching from enable to

95% of VO(Min), Continuous slope (no

slope reversal).

770

875

1200

μs

Soft-Start delay time

Delay time from enable to first switching

pulse.

120

135

150

μs

Soft-Start ramp-up time

From first switching pulse to 95% of

VO(Min), Continuous slope (no slope

reversal).

650

740

1050

μs

DVS total fall time (delay time +

output ramp-down time)

Time to start switching from enable to 5%

of VO(Min), Continuous slope (no slope

reversal).

61.25

68.5

μs

DVS delay time for falling edge

DVS delay time from when STANDBYZ

(SLP_S0#) changes from High to Low,

until the output voltage begins to fall.

1.25

1.5

μs

DVS ramp time for falling edge

From first switching pulse to 5% of

VO(Min), Continuous slope (no slope

reversal). Total ramp time = ((Vout_high -

Vout_low) / slew_rate). For Vout change

= 300 mV.

μs

DVS slew rate for falling edge

DVS falling edge slew rate for VVOUT to

change from the upper target to the lower

target after STANDBYZ (SLP_S0#)

changes from High to Low. Total ramp

time = ((Vout_high - Vout_low) /

slew_rate).

4.5

5.5

mV / μs

DVS total rise time (delay time +

output ramp-rise time)

Time to start switching from enable to

95% of VO(Min), Continuous slope (no

slope reversal).

61.25

68.5

μs

DVS delay time for rising edge

DVS delay time from when STANDBYZ

(SLP_S0#) changes from Low to High,

until the output voltage begins to rise.

1.25

1.5

μs

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