PIFE32251B-R68MS datasheet(35/157 Pages) TI1

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TPS650830

www.ti.com

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Specifications

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ILIM - current limit pin source

current

TA = 25℃

µA

Low-side TCLIM - current limit

temperature coefficient

With respect to 25

℃

4780

ppm/

℃

VILIM - current limit pin setting

voltage range

VILIM = RTRIP*ILIM (usable voltage range

across the operating temperature range)

0.2

Maximum line regulation with

respect to nominal Vout

ULQ/Auto Mode, VVIN = 5.4 V to 21 V,

IOUT = IMAX =7.5 A, Measured at the

regulation point output capacitor with

Kelvin connections made directly from the

regulation point to the differential

feedback pins (FBVR4P - FBVR4N).

-0.5%

0.5%

Maximum load regulation with

respect to nominal Vout

ULQ/Auto Mode, VVIN = 7.4 V, IOUT = 0 A

to IMAX =7.5 A, Measured at the

regulation point output capacitor with

Kelvin connections made directly from the

regulation point to the differential

feedback pins (FBVR4P - FBVR4N).

-0.5%

0.65%

Maximum total output voltage load

transient variation with respect to

nominal Vout

DC and AC, ULQ/Auto Mode, VVIN = 5.4

V to 21 V, IOUT = 0 A to 70% max load,

70% max load to 0 mA and IOUT = 30%

max load to max load, max load to 30%

max load, di/dt = 2.5 A/µs , Measured at

the regulation point output capacitor with

Kelvin connections made directly from the

regulation point to the differential

feedback pins (FBVR4P - FBVR4N).

-5%

Switching frequency

PWM Mode (NVDC# = 3.3 V =

programmed to low switching frequency)

430

500

550

kHz

PWM Mode (NVDC# = GND =

programmed to high switching frequency)

715

800

865

Soft-Start delay time

Delay time from enable to first switching

pulse.

Soft-Start ramp-up time

From first switching pulse to 95% of

VO(Min), Continuous slope (no slope

reversal).

650

740

850

μs

DVS total fall time (delay time +

output ramp-down time)

Time to start switching from enable to 5%

of VO(Min), Continuous slope (no slope

reversal).

61.25

68.5

μs

DVS delay time for falling edge

DVS delay time from when

DDR_VTT_CTRL changes from High to

Low, until the output voltage begins to fall.

1.25

1.5

μs

DVS ramp time for falling edge

From first switching pulse to 5% of

VO(Min), Continuous slope (no slope

reversal). Total ramp time = ((Vout_high -

Vout_low) / slew_rate). For Vout change

= 300 mV

μs

DVS slew rate for falling edge

DVS falling edge slew rate for VVOUT to

change from the upper target to the lower

target after DDR_VTT_CTRL changes

from High to Low. Total ramp time =

((Vout_high - Vout_low) / slew_rate)

4.5

5.5

mV / μs

DVS total rise time (delay time +

output ramp-rise time)

Time to start switching from enable to

95% of VO(Min), Continuous slope (no

slope reversal).

61.25

68.5

μs

DVS delay time for rising edge

DVS delay time from when

DDR_VTT_CTRL changes from Low to

High, until the output voltage begins to

rise.

1.25

1.5

μs

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