PIFE32251B-R68MS datasheet(37/157 Pages) TI1

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TPS650830

www.ti.com

SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016

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Specifications

Electrical Characteristics (continued)

Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient

temperature range of 25°C) (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VR4_Powergood Mask time during

DVS ramp up (exit DVS)

Powergood is kept high and masked

during DVS exit, ramp up, and until 100

µs after the internal reference has

stepped up to the final voltage setting.

ramp-

up + 90

ramp-

up +

100

ramp-

up +

110

μs

VR4_Force PWM time (deglitch

time) during CCM to DCM

transition

PWM is forced for 16 switching cycles

before PFM is enabled turning off the low-

side power MOSFET. Low-side FET

current during each cycle must fall below

the PFM current comparator valley

threshold. Forced PWM allows a fast

transient response and smaller output

voltage ripple during the transition.

cycles

VR4_Force PWM time during DVS

ramp down (enter DVS)

PWM is forced during DVS enter, ramp

down, and until 10 µs after the internal

reference has stepped down to the final

voltage setting. Forced PWM allows a fast

transient response and smaller output

voltage ripple during the transition.

ramp-

down +

ramp-

down +

ramp-

down +

μs

VR4_Force PWM time during DVS

ramp up (exit DVS)

PWM is forced during DVS exit, ramp up,

and until 10 µs after the internal reference

has stepped up to the final voltage

setting. Forced PWM allows a fast

transient response and smaller output

voltage ripple during the transition.

ramp-

up + 9

ramp-

up + 10

ramp-

up + 11

μs

Overtemperature protection

130

145

160

°C

Overtemperature hysteresis

°C

LDO1 POWER

Input voltage

DDRID = 0 V

1.2

Output voltage

DDRID = 0 V, VOUTLDO1 = (VINLDO1S)

/ 2

0.6

Input voltage

DDRID = 3.3 V

1.35

Output voltage

DDRID = 3.3 V, VOUTLDO1 =

(VINLDO1S) / 2

0.675

Input voltage

DDRID = Open

1.1

Output voltage

DDRID = Open, VOUTLDO1 =

(VINLDO1S)/ 2

0.55

Output voltage tolerance - AC and

DC transient load

IOUT ≤ 10 mA, 1.1 V ≤ VINLDO1 ≤ 1.35 V,

(FBLDO1 - FBVR4N) = Output voltage

relative to (VINLDO1S - FBVR4N) / 2,

where VINLDO1S connected to FBVR4P

on the board, Load transient from 0mA to

70%*10 mA, dI/dt = 2.5 A/µs.

-20

IOUT ≤ 1 A, 1.1 V ≤ VINLDO1 ≤ 1.35 V,

(FBLDO1 - FBVR4N) = Output voltage

relative to (VINLDO1S - FBVR4N) / 2,

where VINLDO1S connected to FBVR4P

on the board, Load transient from 0mA to

70%*1A, dI/dt = 2.5 A/µs.

-30

Leakage current

TA = 25°C, VINLDO1 = 1.2 V, Disabled

µA

Bias current at VIN13_SENSE

TA = 25°C Bias current measured when

VINLDO1S is at 1.2 V

µA

Source current limit

Max current from LDO without exceeding

load regulation

1000

Sink current limit

Max current sinked into LDO without

exceeding load regulation (raise output

voltage above programmed value to sink

current into LDO)

1000

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