AT89C5131-RDTIL datasheet(100/176 Pages) ATMEL

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AT89C5131

4136B–USB–09/03

Description

The CPU interfaces to the TWI logic via the following four 8-bit special function regis-

ters: the Synchronous Serial Control register (SSCON; Table 84 and Table 79), the

Synchronous Serial Data register (SSDAT; Table 85), the Synchronous Serial Control

and Status register (SSCS; Table 86) and the Synchronous Serial Address register

(SSADR see Table 87 and Table 78).

SSCON is used to enable SSLC, to program the bit rate (see Table 79), to enable slave

modes, to acknowledge or not a received data, to send a START or a STOP condition

on the TWI bus, and to acknowledge a serial interrupt. A hardware reset disables SSLC.

In write mode, SSCS is used to select the TWI interface and to select the bit rate source.

In read mode, SSCS contains a status code which reflects the status of the TWI logic

and the TWI bus. The three least significant bits are always zero. The five most signifi-

cant bits contain the status code. There are 26 possible status codes. When SSCS

contains F8h, no relevant state information is available and no serial interrupt is

requested. A valid status code is available in SSCS one machine cycle after SI is set by

hardware and is still present one machine cycle after SI has been reset by software.

Table 80 to Table 83 give the status for the master modes and miscellaneous states.

SSDAT contains a byte of serial data to be transmitted or a byte which has just been

received. It is addressable while it is not in process of shifting a byte. This occurs when

TWI logic is in a defined state and the serial interrupt flag is set. Data in SSDAT remains

stable as long as SI is set. While data is being shifted out, data on the bus is simulta-

neously shifted in; SSDAT always contains the last byte present on the bus.

SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which

SSLC will respond when programmed as a slave transmitter or receiver. The LSB is

used to enable general call address (00h) recognition.

Figure 48 shows how a data transfer is accomplished on the TWI bus.

Figure 48. Complete Data Transfer on TWI Bus

The four operating modes are:

•

Master Transmitter

•

Master Receiver

•

Slave Transmitter

•

Slave Receiver

Data transfer in each mode of operation is shown in Figure 49 to Figure 52. These fig-

ures contain the following abbreviations:

S: START condition

R: Read bit (high level at SDA)

W: Write bit (low level at SDA)

SDA

SCL

start

condition

MSB

ACK

acknowledgement

signal from receiver

acknowledgement

signal from receiver

3-8

ACK

stop

condition

clock line held low

while interrupts are serviced

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