AT89C5131-RDTIL datasheet(37/176 Pages) ATMEL

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AT89C5131

4136B–USB–09/03

Table 38. Program Lock bits

Notes:

1. U: unprogrammed or “one” level.

2. P: programmed or “zero” level.

3. X: don’t care

4. WARNING: Security level 2 and 3 should only be programmed after Flash and code

verification.

These security bits protect the code access through the parallel programming interface.

They are set by default to level 4. The code access through the ISP is still possible and

is controlled by the “software security bits” which are stored in the extra Flash memory

accessed by the ISP firmware.

To load a new application with the parallel programmer, a chip erase must be done first.

This will set the HSB in its inactive state and will erase the Flash memory. The part ref-

erence can always be read using Flash parallel programming modes.

Default Values

The default value of the HSB provides parts ready to be programmed with ISP:

•

BLJB: Cleared to force ISP operation.

•

X2: Set to force X1 mode (Standard Mode)

•

OSCON1-0: Set to start with 32 MHz oscillator configuration value.

•

LB2-0: Security level four to protect the code from a parallel access with maximum

security.

Software Registers

Several registers are used, in factory and by parallel programmers, to make copies of

hardware registers contents. These values are used by Atmel ISP (see Section “In-Sys-

tem Programming (ISP)”).

These registers are in the “Extra Flash Memory” part of the Flash memory. This block is

also called ”XAF” or eXtra Array Flash. They are accessed in the following ways:

•

Commands issued by the parallel memory programmer.

•

Commands issued by the ISP software.

•

Calls of API issued by the application software.

Several software registers are described in Table 39.

Program Lock Bits

Protection Description

Security level

LB0

LB1

LB2

No program lock features enabled.

MOVC instruction executed from external

program memory is disabled from fetching code

bytes from any internal memory, EA is sampled

and latched on reset, and further parallel

programming of the Flash and of the EEPROM

(boot and Xdata) is disabled. ISP and software

programming with API are still allowed.

Same as 2, also verify through parallel

programming interface is disabled and serial

programming ISP is disabled.

Same as 3, also external execution is disabled.

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