A25LS512A datasheet(13/43 Pages) AMICC

13 / 43 page

A25LS512A Series

(November, 2014, Version 1.1)

AMIC Technology Corp.

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new

values to be written to the Status Register. Before it can be

accepted, a Write Enable (WREN) instruction must

previously have been executed. After the Write Enable

(WREN) instruction has been decoded and executed, the

device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by

driving Chip Select ( S ) Low, followed by the instruction

code and the data byte on Serial Data Input (DIO).

The instruction sequence is shown in Figure 7. The Write

Status Register (WRSR) instruction has no effect on b6, b5,

b1 and b0 of the Status Register. b6 and b5 are always read

as 0.

Chip Select ( S ) must be driven High after the eighth bit of

the data byte has been latched in. If not, the Write Status

Chip Select ( S ) is driven High, the self-timed Write Status

Write Status Register cycle is in progress, the Status

Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Write Status Register cycle, and is 0

when it is completed. When the cycle is completed, the

Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the

user to change the values of the Block Protect (BP2, BP1,

BP0) bits, to define the size of the area that is to be treated

as read-only, as defined in Table 1. The Write Status

reset the Status Register Write Disable (SRWD) bit in

accordance with the Write Protect (

W ) signal. The Status

W )

signal allow the device to be put in the Hardware Protected

Mode (HPM). The Write Status Register (WRSR) instruction

is not executed once the Hardware Protected Mode (HPM)

is entered.

Figure 7. Write Status Register (WRSR) Instruction Sequence

11 12 13 14 15

Status

High Impedance

Instruction

DIO

MSB

810

01 2 3 4 5 6 7

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