A25LS512A datasheet(8/43 Pages) AMICC

8 / 43 page

A25LS512A Series

(November, 2014, Version 1.1)

AMIC Technology Corp.

Hold Condition

The Hold (

HOLD ) signal is used to pause any serial

communications with the device without resetting the clocking

sequence. However, taking this signal Low does not

terminate any Write Status Register, Program or Erase cycle

that is currently in progress.

To enter the Hold condition, the device must be selected, with

Chip Select (

S ) Low.

The Hold condition starts on the falling edge of the Hold

(

HOLD ) signal, provided that this coincides with Serial Clock

The Hold condition ends on the rising edge of the Hold

(

HOLD ) signal, provided that this coincides with Serial Clock

If the falling edge does not coincide with Serial Clock (C)

being Low, the Hold condition starts after Serial Clock (C)

next goes Low. Similarly, if the rising edge does not coincide

with Serial Clock (C) being Low, the Hold condition ends after

Serial Clock (C) next goes Low. This is shown in Figure 3.

During the Hold condition, the Serial Data Output (DO) is high

impedance, and Serial Data Input (DIO) and Serial Clock (C)

are Don’t Care.

Normally, the device is kept selected, with Chip Select (

S )

driven Low, for the whole duration of the Hold condition. This

is to ensure that the state of the internal logic remains

unchanged from the moment of entering the Hold condition.

If Chip Select (

S ) goes High while the device is in the Hold

condition, this has the effect of resetting the internal logic of

the device. To restart communication with the device, it is

necessary to drive Hold (

HOLD ) High, and then to drive

Chip Select (

S ) Low. This prevents the device from going

back to the Hold condition.

Figure 3. Hold Condition Activation

Hold

Condition

(standard use)

HOLD

Hold

Condition

(non-standard use)

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