RM0312 datasheet(42/275 Pages) STMICROELECTRONICS

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Interrupt controller (ITC)

RM0312

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DocID022352 Rev 3

See Figure 7 for a description of pending interrupt servicing process.

Figure 7. Priority decision process

5.2.2

Interrupt sources

Two interrupt source types are managed by the STM8 interrupt controller:

•

Non-maskable interrupts: RESET and TRAP

•

Maskable interrupts: external interrupts or interrupts issued by internal peripherals

Non-maskable interrupt sources

Non-maskable interrupt sources are processed regardless of the state of bits I1 and I0 of the

CCR register (see Figure 6). PC, X, Y, A and CCR registers are stacked only when a TRAP

interrupt occurs. The corresponding vector is then loaded in the PC register and bits I1 and

I0 of the CCR register are set to disable interrupts (level 3).

•

TRAP (non-maskable software interrupt)

This software interrupt source is serviced when the TRAP instruction is executed. It is

serviced according to the flowchart shown in Figure 6.

A TRAP interrupt does not allow the processor to exit from Halt mode.

•

RESET

The RESET interrupt source has the highest STM8 software and hardware priorities.

This means that all the interrupts are disabled at the beginning of the reset routine.

They must be re-enabled by the RIM instruction (see Table 12: Dedicated interrupt

instruction set).

A RESET interrupt allows the processor to exit from Halt mode.

See RESET chapter for more details on RESET interrupt management.

PENDING

SOFTWARE

Different

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

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