RM0312 datasheet(68/275 Pages) STMICROELECTRONICS

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Power management

RM0312

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DocID022352 Rev 3

9.2

Managing the clock for low consumption

9.2.1

Slowing the system clocks

In run mode, choosing the clock frequency is very important to ensure the best compromise

between performance and consumption. The selection is done by programming the

CLK_CKDIVR register. Refer to 8.4.1: Clock divider register (CLK_CKDIVR) on page 63.

Note:

In applications where the MCU can be halted for certain periods, the power consumption

can be minimized by keeping a fast clock (high performance execution) during active

periods, in order to reduce the ratio between active periods and Halt (that is “zero”-

consumption) periods.

9.2.2

Peripheral clock gating

For additional power saving you can use Peripheral Clock Gating (PCG). This can be done

at any time by selectively enabling or disabling the fMASTER clock connection to individual

peripherals. Refer to 8.4.2: Peripheral clock gating register 1 (CLK_PCKENR1) on page 64

and 8.4.3: Peripheral clock gating register 2 (CLK_PCKENR2) on page 64.

These settings are effective in both Run and Wait modes. Refer to 8.1.1: Peripheral clock

gating (PCG) on page 62.

Each PCG state represents a specific power or low power level.

9.3

Switching peripherals off

Any of the MCU peripherals can be deactivated when they are not used in order to minimize

power consumption. This is true for both analog and digital peripherals.

Each ON/OFF combination represents a specific power or low power level.

Each of the peripherals can be switched off by a dedicated control bit:

•

Single Wire Interface Module (SWIM) by the SWD bit in the SWIM_CSR register

•

Auto-Wakeup Unit (AWU) by the AWUEN bit in the AWU_CSR register

•

Beeper by the BEEPEN bit in the AWU_CSR register

•

Timers by the CEN bits in the TIMx_CR1 registers

•

I2C by the PE bit in the I2C_CR1 register

•

SPI by the SPE bit in the SPI_CR1

•

USART by the USART_CR2 register

•

WWDG by the WWDG_CR register

•

ProxSense by the PXS_CR1 register

Note:

These control bits should be written only when the corresponding peripheral clock is

enabled

Once the IWDG is activated, it cannot be disabled except with a reset.

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