AN557 datasheet(22/52 Pages) STMICROELECTRONICS

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AN557 APPLICATION NOTE

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POWER STAGE

The simplified diagram of the output stage is shown in the fig. 27.

The power stage and the circuit connected with it are by far the most important and critical components

when one wants to obtain good performance at high switching frequency.

The power transistor must have excellent characteristics from the point of view of both the switching speed

and the robustness.

The transistor DMOS, with its intrinsic characteristics of elevated speed, no second breakdown phenomenom and

easy driving proves to be particularly suitable for this type of application that normally works at high frequency.

For a properly driving of the DMOS gate it is necessary to use an external bootstrap capacitor. When the

voltage Vs is low the Cboot capacitor is charged through the internal diode D1, at the value of voltage

equal to that of Vstart, which is about 12V; the next step oversees that Q3 is turned off, Q2 is driven in

gate by Q1 so that Q1 can go in saturation, and its source can go up rise towards Vi.

Cboot maintains its charge and guarantees a voltage equal Vi+12V at the gate of Q7, so that can enter

into region of low resistance.

At this point the diode D1 turns on to be inversely polarized, disconnecting the 12V section from that of

the driving power stage.

When Q2 is ON the driven current of the power stage requires from the bootstrap capacitor a typical cur-

rent of 400uA.

When Q2 is Off a current of 2.5mA is required to mantain Q2 in that state. This current however is not

delivered from the bootstrap capacitor, but rather from the internal regulator of 12V, while the output cur-

rent flowing in the freewheeling diode. The circuit described is capable of obtaining commutation, rise and

fall time, a typical value of 50ns.

In principle, it would have been feasible to reduce furthermore the commutation time whithout any reliabil-

ity problems.

This was not believed to be advantageous since it would not have been of any benefit if one thinks of the

trr time of the catch diode (with trise of 50ns also the Schottky diodes begin to show limitations) and of the

conseguent increase of different disturbances caused bt too higly elevated dI/dt. The following table

shows the main features of the DMOS transistor.

Figure 28. Gate-charge curve for the power

Table 1.

BVDSS > 60V

at ID = 1mA

VGS = 0V

RDS(ON) = 100m

Ω

at ID = 10A

Tj = 25

°CVGS = 10V

RDS(ON) = 150m

Ω

at ID = 10A

Tj = 150

°CVGS = 10V

VTH = 3V

at ID = 1mA

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