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376 EMBEDDED PROCESSOR

starting the pending bus cycle before the present

bus cycle is finished A non-pipelined bus cycle

gives the highest bus performance by executing ev-

ery bus cycle in two processor clock cycles For

maximum design flexibility the address pipelining

option is selectable on a cycle-by-cycle basis

The processor’s bus cycle is the basic mechanism

for information transfer either from system to proc-

essor or from processor to system 80376 bus cy-

cles perform data transfer in a minimum of only two

clock periods On a 16-bit data bus the maximum

80376 transfer bandwidth at 16 MHz is therefore

16 Mbytessec However any bus cycle will be ex-

tended for more than two clock periods if external

hardware withholds acknowledgement of the cycle

The 80376 can relinquish control of its local buses

to allow mastership by other devices such as direct

memory access (DMA) channels

When relin-

quished HLDA is the only output pin driven by the

80376

providing near-complete isolation of the

processor from its system (all other output pins are

in a float condition)

41 Signal Description Overview

Ahead is a brief description of the 80376 input and

output signals arranged by functional groups

The signal descriptions sometimes refer to AC tim-

ing parameters such as ‘‘t25 Reset Setup Time’’ and

‘‘t26 Reset Hold Time’’ The values of these parame-

ters can be found in Tables 64 and 65

CLOCK (CLK2)

CLK2 provides the fundamental timing for the

80376 It is divided by two internally to generate the

internal processor clock used for instruction execu-

tion

The internal clock is comprised of two

240182 – 17

Figure 42 CLK2 Signal and Internal Processor Clock

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