HT47C20 datasheet(26/56 Pages) HOLTEK

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HT47C20

January 18, 2000

The bit4~bit7 of ADCR decides which resistor

and capacitor compose an oscillation circuit and

input to TMRBH and TMRBL.

The TN0, TN1 and TN2 bits of TMRC define

the clock source of timer A. It is recommended

that the clock source of timer A use the system

clock, instruction clock or RTC prescaler clock.

The TON bit (bit 4 of TMRC) is set ²1² the timer

A and timer B will start counting until timer A

or timer B overflows, the timer/event counter

generates the interrupt request flag (TF ; bit 4

of INTC1) and the timer A and timer B stop

counting and reset the TON bit to ²0² at the

same time.

If the TON bit is ²1², the TMRAH, TMRAL,

TMRBH and TMRBL cannot be read or written

to. Only when the timer/event counter is off and

when the instruction ²MOV² is used could those

four registers be read or written to.

Example for RC type AD converter mode (Timer A overflow):

clr tmrc

clr adcr.1

; set timer mode

clr intc1.4

; clear timer/event counter interrupt request flag

mov a, low (65536-1000)

; give timer A initial value

mov tmrbl, a

; count 1000 time and then overflow

mov a, high (65536-1000)

mov tmrbh, a

mov a, 00010010b

; RS0~CS0; set RC type ADC mode; set Timer A overflow

mov adcr,a

mov a, 00h

; give timer B initial value

mov tmrbl, a

mov a, 00h

mov tmrbh, a

mov a, 00110000b

; timer A clock source=T1 and timer on

mov tmrc, a

p10:

clr wdt

snz intcl.4

; polling timer/event counter interrupt request flag

jmp p10

clr intcl.4

; clear timer/event counter interrupt request flag

; program continue

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