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HT47C20 Folha de dados(PDF) 18 Page - Holtek Semiconductor Inc

Nome de Peças HT47C20
Descrição Electrónicos  8-Bit Microcontroller
PDF  56 Pages
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Fabricante Electrônico  HOLTEK [Holtek Semiconductor Inc]
Página de início  http://www.holtek.com
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HT47C20
18
January 18, 2000
Real time clock - RTC
The real time clock (RTC) is operated in the
same manner as the time base that is used to
supply a regular internal interrupt. Its
time-out period ranges from fs/28 to fs/215 by
software programming . Writing data to RT2,
RT1 and RT0 (bits 2, 1, 0 of RTCC;09H) yields
various time-out periods. If the RTC time-out
occurs, the related interrupt request flag (RTF;
bit 6 of INTC0) is set. But if the interrupt is en-
abled, and the stack is not full, a subroutine call
to location 0CH occurs. The real time clock
time-out signal can also be applied to be a clock
source of timer/event counter, so as to get a lon-
ger time-out period.
RT2 RT1 RT0
RTC Clock Divided
Factor
000
28
001
29
010
210
011
211
100
212
101
213
110
214
111
215
Power down operation - HALT
The HALT mode is initialized by the HALT in-
struction and results in the following.
· The system oscillator will turn off but the
WDT oscillator or RTC oscillator keeps run-
ning (if the WDT oscillator or the real time
clock is selected).
· The contents of the on-chip RAM and regis-
ters remain unchanged.
· The WDT will be cleared and recounted again
(if the WDT clock comes from the WDT oscil-
lator or the real time clock oscillator).
· All I/O ports maintain their original status.
· The PD flag is set and the TO flag is cleared.
· LCD driver is still running by mask option (if
the WDT OSC or RTC OSC is selected).
The system can leave the halt mode by means of
an external reset, an interrupt, an external fall-
ing edge signal on port A or a WDT overflow. An
external reset causes a device initialization and
the WDT overflow performs a ²warm reset².Ex-
amining the TO and PD flags, the reason for
chip reset can be determined. The PD flag is
cleared when the system power-up or executing
the CLR WDT instruction and is set when the
HALT instruction is executed. The TO flag is set
if a WDT time-out occurs, it causes a wake-up
that only resets the PC and SP, the others main-
tain their original status.
The port A wake-up and interrupt methods can
be considered as a continuation of normal exe-
cution. Each bit in port A can be independently
selected to wake up the device by mask option.
Awakening from an I/O port stimulus, the pro-
gram will resume execution of the next instruc-
tion. If awakening from an interrupt, two
sequences may happen. If the related interrupt
is disabled or the interrupt is enabled but the
stack is full, the program will resume execution
at the next instruction. If the interrupt is en-
abled and the stack is not full, the regular inter-
rupt response takes place.
If an interrupt request flag is set to ²1² before
entering the halt mode the wake-up function of
the related interrupt will be disabled.
8
f s /2
D i v i der
f s
8 t o 1
Mu x .
P r e sca l e r
RT 2
RT 1
RT 0
RT C I n t e r r u p t
8
15
f s /2 ~ f s /2
Real time clock



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