ADS930

10

SBAS059A

DC-COUPLED INTERFACE CIRCUIT

Figure 5 illustrates an example of a DC-coupled interface

circuit using one high-speed op amp to level-shift the ground-

referenced input signal. This serves to condition it for the

input requirements of the ADS930. With a +3V supply the

input signal swings 1Vp-p centered around a typical com-

mon-mode voltage of +1.5V. This voltage can be derived

from the internal bottom reference (REFB) and then fed

of the wideband noise to ground. Depending on the config-

bottom reference. Considerations for the selection of a

proper op amp should include its output swing, input com-

mon-mode range, and bias current. This circuit can easily be

modified for a +5V operation of the ADC, requiring a higher

common-mode level (+2.5V).

INTERNAL REFERENCE

The ADS930 features an internal reference that provides

fixed reference voltages for the internal stages. As shown in

Figure 6, each end of the resistor ladder (REFT and REFB)

are driven by a buffer amplifier. The ladder has a nominal

resistance of 4k

Ω (±15%). The two outputs of the buffers are

brought out at pin 21 (LpBy) and pin 25 (LnBy), primarily

to connect external bypass capacitors, typically 0.1

µF. They

will shunt the high frequency switching noise that is fed

back into the reference circuit and improve the performance.

The buffers can drive limited external loads, for example

level-shifting of the converter’s interface circuit. However,

the current draw should be limited to approximately 1mA.

Derived from the top reference of +1.75V is an additional

voltage of +1.0V. Note that this voltage, available on pin 23,

is not buffered and care should be taken when external loads

are applied. In normal operation, this pin is left unconnected

and no bypassing components are required.

CLOCK INPUT

The clock input of the ADS930 is designed to accommodate

either +5V or +3V CMOS logic levels. To drive the clock

input with a minimum amount of duty cycle variation and

support the maximum sampling rate (30MSPS), high speed

or advanced CMOS logic should be used (HC/HCT,

AC/ACT). When digitizing at high sampling rates, a 50%

duty cycle, along with fast rise and fall times (2ns or less),

FIGURE 6. Internal Reference Structure and Recommended Reference Bypassing.

ADS930

2.8k

Ω

2k

Ω

2k

Ω

+1.75V

+1.25V

2.1k

Ω

0.1µF

REFT

REFB

LpBy

21

23

26

25

+1V

REF

0.1µF

LnBy

0.1µF

CM

FIGURE 5. Single-supply, DC-coupled Interface Circuit.

OPA680

V

IN

+5V

R

F

V

I = 250µA

0.1µF

IN

CM

REFB

+1.25V

R

S

R

IN

+3V

R

1

R

2

V

OS

0.1µF

22pF

0.1µF

ADS930

IN