ADS930EG4 datasheet(8/16 Pages) TI1

8 / 16 page

ADS930

SBAS059A

FIGURE 1. Input Track/Hold Configuration with Timing

Signals.

FIGURE 2. Pipeline ADC Architecture.

THEORY OF OPERATION

The ADS930 is a high speed sampling ADC that utilizes a

pipeline architecture. The fully differential topology and

digital error correction guarantee 8-bit resolution. The track/

hold circuit is shown in Figure 1. The switches are con-

trolled by an internal clock which has a non-overlapping two

phase signal,

φ1 and φ2. At the sampling time the input

signal is sampled on the bottom plates of the input capaci-

tors. In the next clock phase,

φ2, the bottom plates of the

input capacitors are connected together and the feedback

capacitors are switched to the op amp output. At this time the

charge redistributes between CI and CH, completing one

track/hold cycle. The differential output is a held DC repre-

sentation of the analog input at the sample time. In the

normal mode of operation, the complementary input is tied

to the common-mode voltage. In this case, the track/hold

circuit converts a single-ended input signal into a fully

differential signal for the quantizer. Consequently, the input

signal gets amplified by a gain or two, which improves the

signal-to-noise performance. Other parameters such as small-

signal and full-power bandwidth, and wideband noise are

also defined in this stage.

φ1

φ2

φ1

φ2

φ1

φ2

φ1

φ2

(Opt.)

OUT

Op Amp

Bias

Op Amp

Bias

Input Clock (50%)

Internal Non-overlapping Clock

–

B1 (MSB)

B8 (LSB)

2-Bit

DAC

2-Bit

Flash

Input

T/H

Digital Delay

2-Bit

DAC

2-Bit

Flash

Digital Delay

2-Bit

Flash

Digital Delay

2-Bit

DAC

2-Bit

Flash

Digital Delay

STAGE 1

STAGE 2

STAGE 6

STAGE 7

–

(Opt.)

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