ADS930

9

SBAS059A

R

1

1k

Ω

OPA680

V

IN

R

F

402

Ω

R

S

50

Ω

R

G

402

Ω

V

CM

C

1

0.1µF

0.1µF

IN

IN

CM

+5V

+3V

C

G

0.1µF

22pF

ADS930

R

P

402

Ω

The pipelined quantizer architecture has 7 stages with each

stage containing a two-bit quantizer and a two bit Digital-

to-Analog Converter (DAC), as shown in Figure 2. Each

two-bit quantizer stage converts on the edge of the sub-

clock, which is the same frequency of the externally applied

clock. The output of each quantizer is fed into its own delay

line to time-align it with the data created from the subse-

quent quantizer stages. This aligned data is fed into a digital

error correction circuit which can adjust the output data

based on the information found on the redundant bits. This

technique provides the ADS930 with excellent differential

linearity and guarantees no missing codes at the 8-bit level.

The ADS930 includes an internal reference circuit that

provides the bias voltages for the internal stages (for details

see “Internal Reference”). A midpoint voltage is established

by the built-in resistor ladder which is made available at pin

26 “CM”. This voltage can be used to bias the inputs up to

the recommended common-mode voltage or to level shift

the input driving circuitry. The ADS930 can be used in both

a single-ended or differential input configuration. When

operated in single-ended mode, the reference midpoint (pin

26) should be tied to the inverting input, pin 24.

To accommodate a bipolar signal swing, the ADS930 oper-

from the internal references. Due to the symmetric resistor

and bottom reference voltage. The following equation can

be used for calculating the common-mode voltage level:

(1)

APPLICATIONS

DRIVING THE ANALOG INPUTS

Figure 3 shows an example of an ac-coupled, single-ended

interface circuit using high-speed op amps which operate on

dual supplies (OPA650, OPA658). The mid-point reference

filter with the –3dB frequency set at

and can be set freely. The values shown in Figure 3 corre-

spond to a corner frequency of 1.6kHz.

Figure 4 depicts a circuit that can be used in single-supply

applications. The mid-reference biases the op amp up to the

non-inverting op amp input is set to +1V/V. As a result, the

transfer function is modified to

a high-pass filter. At the same time, the input impedance is

the capacitive load to avoid gain peaking or even oscillation.

It can also be used to establish a defined bandwidth to reduce

the wideband noise. Its value is usually between 10

Ω and

100

Ω.

FIGURE 4. Interface Circuit Example Using the Voltage Feedback Amplifier OPA680.

FIGURE 3. AC-Coupled Driver.

402

Ω

OPA650

OPA658

V

IN

402

Ω

R

1

1k

Ω

V

CM

C

1

0.1µF

0.1µF

IN

IN

CM

+5V

10

Ω

–5V

+3V

ADS930