AS8506 datasheet(30/89 Pages) AMSCO

30 / 89 page

AS8506 – 30

ams Datasheet, Confidential:2013-Sep [1-00]

De tail ed De sc rip t ion

At the end of the Diagnosis phase, if trigger signal is ‘High’ then

it enters into Balance phase. If trigger signal is ‘Low’ it enters

into WAIT mode.

The Diagnosis phase without the cell voltage measurement

with SAR ADC is called Compare phase.

Balance Phase

The Balance phase is basically a charging cycle in case of active

balancing and a discharging cycle in case of passive balancing.

The Balance phase is divided into 7 time slots. The device will

move through all 7 time slots irrespective of number of cells

connected to the device. This is done to keep synchronization

between each module in case of battery stack system. One time

slot is assigned to each cell (sequential order) for charging or

discharging. The period of time slots is programmable (see

“Status Registers” on page 52).

In each time slot, following operations are done.

• Check CVT_NOK flag status. If CVT_NOK flag is set, then

no operation is done till time slot is over. If CVT_NOK flag

is not set, then move to the next step.

• Based on Diagnosis phase results, shuttle switch

corresponding to current time slot cell is switched ON for

charging that cell in case of active balancing, and

discharging in case of passive balancing.

• The PWM generator is enabled and PWM driver start

driving the Flyback converter FET (external component)

in case of active balancing. The PWM frequency and duty

cycles are factory programmable and also register

controllable. In case of stack system, the bottom module

PWM driver is enabled when there is a request of charging

or discharging from top module on FD_OUT pin.

• At the end of the current time slot, stop the PWM

generator and then open the corresponding shuttle

switches. The device moves to the next time slot.

In the Balance phase, at any point, if the trigger input goes ‘Low’,

then the device suspends balancing operation and enters into

WAIT mode.

Sleep Mode

This is the least power consumption mode of AS8506. In this

mode only pre-reg is ON, rest all analog blocks are OFF and

digital clock is disabled. Only a digital wake detection circuit is

active. The device enters into this mode when there is no trigger

from microcontroller for time greater than WAIT mode timeout

period.

Wait Mode

This mode is a transition mode, where the device waits for

command on TRIG_IN pin either from microcontroller, (or) from

below module in case of stack system. The device will be in this

state for TWMODE_TOUT period. After the timeout, the device

AS8506 Folha de dados(PDF) 30 Page - ams AG

AS8506 Folha de dados(HTML) 30 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

Folha de dados Download

Ligação URL