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AS8506 Folha de dados(PDF) 26 Page - ams AG |
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AS8506 Folha de dados(HTML) 26 Page - ams AG |
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26 / 89 page ![]() AS8506 – 26 ams Datasheet, Confidential:2013-Sep [1-00] De tail ed De sc rip t ion AS8506 System Operation The AS8506 battery stack system can be set up by configuring one AS8506 device as ‘Master’ and the rest as ‘Slave’ devices. The AS8506 Master device is connected to the microcontroller, and the Slave devices are connected to Master through a daisy-chain of 3-wire customized SPI protocol. The microcontroller can communicate to the Slave devices through the Master. On power-up of the system, the microcontroller must assign an address to all AS8506 devices including the Master. The microcontroller can assign the address to AS8506 devices by initiating the address allocation process, by writing a top most Slave device address into dadd_for_allc_reg register of Master and then writing ‘07’ data into spi3_cmd_reg. Once the address allocation process is successful, the microcontroller can start the cell balancing. If cell balancing or check status command is not triggered by the microcontroller, after WAIT mode timeout period all devices enter into SLEEP mode. The complete system communication procedure is explained below. • The microcontroller gives wake pulse on WAKE_IN to bring the Master and Slaves in NORMAL mode. • After the wake-up time period, the microcontroller (μC) sends the reference voltage digital code to the Master device through a 4-wire SPI. • After receiving the digital reference code from μC, the Master device initiates a 3-wire custom SPI operation to send the digital reference code to the Slave devices. • The microcontroller waits for the 3-wire SPI operation time period. After the 3-wire SPI time period, it initiates the cell balancing through TRIG_IN. The balancing will continue as long as TRIG_IN is ‘High’. • The microcontroller can change the reference value at any time by making TRIG_IN ‘Low’ and initiating a 4-wire SPI with new value of reference code. From here on, the procedure is same as from point 3. • The balance done is indicated on BD_OUT pin. • The failure in the 3-wire SPI operation is indicated on CVT_NOK_OUT pin. |
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