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SPEAR320-2 Folha de dados(PDF) 65 Page - STMicroelectronics

Nome de Peças SPEAR320-2
Descrição Electrónicos  Embedded MPU with ARM926 core, optimized for factory automation and consumer applications
PDF  73 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR320-2 Folha de dados(HTML) 65 Page - STMicroelectronics

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SPEAr320
Timing requirements
Doc ID 16755 Rev 5
65/73
7.12.2
SPI master mode timings (clock phase = 1)
Figure 26.
SPI master mode external timing (clock phase = 1)
Table 48.
Timing requirements for SPI master mode (clock phase = 1)
No.
Parameters
Min
Max.
Unit
13
tsu(DIV-CLKL)
Setup time, MISO (input) valid
before SSP_CLK (output) rising
edge
Clock
Polarity = 0
-0.4
-0.3
ns
14
tsu(DIV-CLKH)
Setup time, MISO (input) valid
before SSP_CLK (output) falling
edge
Clock
Polarity = 1
-0.4
-0.3
ns
15
th(CLKL-DIV)
Hold time, MISO (input)valid after
SSP_CLK (output) rising edge
Clock
Polarity = 0
0.9
1.7
ns
16
th(CLKH-DIV)
Hold time, MISO (input) valid after
SSP_CLK (output) falling edge
Clock
Polarity = 1
0.9
1.7
ns
Table 49.
Switching characteristics over recommended operating conditions for
SPI master mode (clock phase = 1)
No.
Parameters
Min
Max
Unit
17
td(CLKH-DOV)
Delay time, SSP_CLK (output) falling
edge to MOSI (output) transition
Clock
Polarity = 0
-3.1
2.2
ns
18
td(CLKL-DOV)
Delay time, SSP_CLK (output) rising
edge to MOSI (output) transition
Clock
Polarity = 1
-3.1
2.2
ns
19
td(ENL-CLKH/L)
Delay time, SSP_CSn (output) falling edge to first
SSP_CLK (output) rising or falling edge
T/2
ns
20
td(CLKH/L-ENH)
Delay time, SSP_CLK (output) rising or falling
edge to SSP_CSn (output) rising edge
Tns



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