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SPEAR320-2 Folha de dados(PDF) 63 Page - STMicroelectronics

Nome de Peças SPEAR320-2
Descrição Electrónicos  Embedded MPU with ARM926 core, optimized for factory automation and consumer applications
PDF  73 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR320-2 Folha de dados(HTML) 63 Page - STMicroelectronics

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SPEAr320
Timing requirements
Doc ID 16755 Rev 5
63/73
7.12
SSP timing characteristics
This module provides a programmable length shift register which allows serial
communication with other SSP devices through a 3 or 4 wire interface (SSP_CLK,
SSP_MISO, SSP_MOSI and SSP_CSn). The SSP supports the following features:
●
Master/Slave mode operations
●
Chip-selects for interfacing to multiple slave SPI devices.
●
3 or 4 wire interface (SSP_SCK, SSP_MISO, SSP_MOSI and SSP_CSn)
●
Single interrupt
●
Separate DMA events for SPI Receive and Transmit
●
16-bit shift register
●
Receive buffer register
●
Programmable character length (2 to 16 bits)
●
Programmable SSP clock frequency range
●
8-bit clock pre-scaler
●
Programmable clock phase (delay or no delay)
●
Programmable clock polarity
Note:
The following tables and figures show the characterization of the SSP using the SPI
protocol.
T = Tc(CLK) = SSP_CLK period is equal to the SSP module master clock divided by a
configurable divider.
Figure 24.
SSP_CLK timings
Table 45.
Timing requirements for SSP (all modes)
No.
parameters
Min
Max
Unit
1Tc(CLK)
Cycle time, SSP_CLK
24
–
ns
2Tw(CLKH)
Pulse duration, SSP_CLK high
0.49*To
0.51*To
ns
3Tw(CLKL)
Pulse duration, SSP_CLK low
0.49*To
0.51*To
ns



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