CDCM7005_13 datasheet(27/45 Pages) TI

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S0081-01

Power_Down

Lock_Out

Lock_In

100 A

(Lock)

100 A

(Out-of-Lock)

80kW

5pF

PLL_LOCK

Output

=0.55V

high

=0.35V

low

Out

=1/C

Out

´ ´

Example:

forI=110 A,C=10nF,V

=3.3V,

andV

=0.55

Vcc=1.8V

t=164 s

high

out

S0080-01

Power_Down

Lock_Out

Lock_In

80kW

5pF

PLL_LOCK

Output

Lock

DigitalLockDetection

=0.55V

high

=0.35V

low

Out-of-Lock

Out

CDCM7005

www.ti.com

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

Digital vs Analog Lock

Figure 18 and Figure 19 show the circuit for the digital and analog lock. The analog lock operates with an

external load capacitor.

When selecting the digital PLL lock option, PLL_LOCK will possibly jitter several times between lock and out of

lock until a stable lock is detected. A single low-to-high step can be reached with a wide lock detect window and

high number of successive clock cycles. PLL_LOCK returns to out of lock if just one cycle is outside the lock

detect window or a frequency offset occurs.

Figure 18. Digital Lock-Detect

When selecting the analog PLL Lock option, the high-pulses load the external capacitor via the internal 110-µA

current source until logic high-level is reached. Therefore, more time is needed to detect logic high level, but

jittering of PLL_LOCK will be suppressed in case of digital lock. The time PLL_LOCK needs to return to out of

lock depends on the level of VOut, when the current source starts to unload the external capacitor.

Figure 19. Analog Lock-Detect

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