CDCM7005_13 datasheet(9/45 Pages) TI

9 / 45 page

CDCM7005

www.ti.com

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Load see Figure 13, all outputs have the

same divider ratio

tsk(o)

LVPECL output skew(5)

Load see Figure 13, outputs have

different divider ratios

tr / tf

Rise and fall time

20% to 80% of VOUTPP, see Figure 9

120

170

220

Input capacitance at VCXO_IN,

1.5

VCXO_IN

LVCMOS-TO-LVPECL

Output skew between LVCMOS and

Cross point to VCC/2; load,

tsk(P_C)

1.7

2.4

LVPECL outputs, see (7) and Figure 10

see Figure 12 and Figure 13

PLL ANALOG LOCK

IOH

High-level output current

VCC = 3.6 V, VO = 1.8 V

–110

µA

IOL

Low-level output current

VCC = 3.6 V, VO = 1.8 V

110

µA

High-impedance state output current

IOZH LOCK

VO = 3.6 V (PD is set low)

µA

for PLL LOCK output(8)

High-impedance state output current

IOZL LOCK

VO = 0 V (PD is set low)

±5

µA

for PLL LOCK output(8)

VIT+

Positive input threshold voltage

VCC = min to max

VCC×0.55

VIT–

Negative input threshold voltage

VCC = min to max

VCC×0.35

PHASE DETECTOR

fCPmax

Maximum charge pump frequency

Default PFD pulse width delay

100

MHz

CHARGE PUMP

Charge pump sink/source current

ICP

VCP = 0.5 VCC_CP

±0.2

±3

range (9)

ICP3St

Charge pump 3-state current

0.5 V < VCP < VCC_CP – 0.5 V

VCP = 0.5 VCC_CP, internal reference

10%

resistor, SPI default settings

ICPA

ICP absolute accuracy

VCP = 0.5 VCC_CP, external reference

resistor 12 k

Ω (1%) at I_REF_CP, SPI

default settings

0.5 V < VCP < VCC_CP – 0.5 V, SPI

ICPM

Sink/source current matching

2.5%

default settings

IVCPM

ICP vs VCP matching

0.5 V < VCP < VCC_CP – 0.5 V

(7)

The phase of LVCMOS is lagging in reference to the phase of LVPECL.

(8)

Lock output has an 80-k

Ω pulldown resistor.

(9)

Defined by SPI settings.

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