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AD9430

Rev. E | Page 13 of 44

PIN 1

AD9430

LVDS PINOUT

TOP VIEW

(Not to Scale)

26 27 28 29 30 31 32 33 34 35 36

37 38 39 40 41

42 43 44 45 46 47

48 49 50

100

DNC

AGND

LVDSBIAS

AVDD

AGND

SENSE

VREF

AGND

AVDD

AGND

AVDD

AGND

VIN+

VIN–

AGND

AVDD

AGND

NOTES

1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF

THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF

THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL

TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE

SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

DRVDD

DRGND

D8+

D8–

D7+

D7–

D6+

D6–

DRGND

D5+

D5–

DCO+

DCO–

DRVDD

DRGND

D4+

D4–

D3+

D3–

D2+

D2Ð

DRVDD

DRGND

D1+

D1–

Figure 5. LVDS Mode Pin Configuration

Table 8. LVDS Mode Pin Function Descriptions

Pin Number

Mnemonic

Description

Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential,

GND sets fS = 1.536 V p-p differential.

2, 42 to 46

DNC

Do Not Connect.

Control Pin for CMOS Mode. Tie low when operating in LVDS

mode.

4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91,

92, 93, 96, 97, 100

AGND1

Analog Ground.

Output Mode Select. GND = dual-port CMOS; AVDD = LVDS.

Data Format Select. GND = binary, AVDD = twos complement.

LVDSBIAS

Set Pin for LVDS Output Current. Place 3.74 kW resistor

terminated to ground.

8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95,

AVDD2

3.3 V Analog Supply.

98, 99

SENSE

Reference Mode Select Pin. Float for internal reference

operation.

VREF

1.235 V Reference I/O—Function Dependent on SENSE.

VIN+

Analog Input—True.

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