AD9430_10 datasheet(8/44 Pages) AD

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AD9430

Rev. E | Page 8 of 44

SWITCHING SPECIFICATIONS

AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.

Table 4.

Test

AD9430-170

AD9430-210

Parameter (Conditions)

Temp

Level

Min

Typ

Max

Min

Typ

Max

Unit

Maximum Conversion Rate1

Full

170

210

MSPS

Minimum Conversion Rate1

Full

MSPS

CLK+ Pulse Width High (tEH)1

Full

12.5

CLK+ Pulse Width Low (tEL)1

Full

12.5

DS Input Setup Time (tSDS)2

Full

–0.5

DS Input Hold Time (tHDS)2

Full

1.75

OUTPUT (CMOS Mode)

Valid Time (tV)

Full

Propagation Delay (tPD)

Full

3.8

Rise Time (tR) (20% to 80%)

25°C

Fall Time (tF) (20% to 80%)

25°C

DCO Propagation Delay (tCPD)

Full

3.8

Data to DCO Skew (tPD to tCPD)

Full

–0.5

+0.5

–0.5

+0.5

Interleaved Mode (A, B Latency)

Full

14, 14

Cycles

Parallel Mode (A, B Latency)

Full

15, 14

Cycles

OUTPUT (LVDS Mode)

Valid Time (tV)

Full

2.0

Propagation Delay (tPD)

Full

3.2

4.3

3.2

4.3

Rise Time (tR) (20% to 80%)

25°C

0.5

Fall Time (tF) (20% to 80%)

25°C

0.5

DCO Propagation Delay (tCPD)

Full

1.8

2.7

3.8

1.8

2.7

3.8

Data to DCO Skew (tPD – tCPD)

Full

0.2

0.5

0.8

0.2

0.5

0.8

Latency

Full

Cycles

APERTURE DELAY (tA)

25°C

1.2

APERTURE UNCERTAINTY (Jitter, tJ)

25°C

0.25

ps rms

OUT OF RANGE RECOVERY TIME (CMOS and LVDS)

25°C

Cycles

1 All ac specifications tested by differentially driving CLK+ and CLK−.

2 DS inputs used in CMOS mode only.

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