DNC3X3125 datasheet(6/32 Pages) AGERE

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DNC3X3125

Advance Data Sheet

10/100 Mbits/s Ethernet Transceiver Macrocell

March 2000

Signal Information

Signal Descriptions

Table 1. MII/5-Bit Serial Interface Signals

Signal

Type

Name/Description

MCOL

Collision Detect. This signal signifies in half-duplex mode that a collision has occurred on

the network. MCOL is asserted high whenever there is transmit and receive activity on the

UTP media. MCOL is the logical AND of MTX_EN and receive activity, and is an asynchro-

nous output. When SER_SEL_PIN is high and in 10Base-T mode, MCOL indicates the

jabber timer has expired.

MCRS

Carrier Sense. When CRS_SEL is low, this signal is asserted high when either the

transmit or receive medium is nonidle. This signal remains asserted throughout a collision

condition. When CRS_SEL is high, MCRS is asserted on receive activity only. CRS_SEL is

set via the MII management interface or the CRS_SEL signal.

MRXCLK

Receive Clock. 25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output in 10 Mbits/s

nibble mode, and 10 MHz in 10 Mbits/s serial mode. MRXCLK has a worst-case 35/65 duty

cycle. MRXCLK provides the timing reference for the transfer of MRX_DV, MRXD, and

MRX_ER signals.

MRXD[3:0]

Receive Data. 4-bit parallel data outputs that are synchronous to MRXCLK. When

MRX_ER is asserted high in 100 Mbits/s mode, an error code will be presented on

MRXD[3:0] where appropriate. The codes are as follows:

Packet errors: ERROR_CODES = 2h.

Link errors: ERROR_CODES = 3h. (Packet and link error codes will only be repeated if

registers [29.9] and [29.8] are enabled.)

Premature end errors: ERROR_CODES = 4h.

Code errors: ERROR_CODES = 5h.

When SER_SEL_PIN is active-high and 10 Mbits/s mode is selected, MRXD[0] is used for

data output and MRXD[3:1] are 3-stated.

MRX_DV

Receive Data Valid. When this signal is high, it indicates the DNC3X3125 is recovering

and decoding valid nibbles on MRXD[3:0], and the data is synchronous with MRXCLK.

MRX_DV is synchronous with MRXCLK. This signal is not used in serial 10 Mbits/s mode.

MRX_ER

Receive Error. When high, MRX_ER indicates the DNC3X3125 has detected a coding

error in the frame presently being received. MRX_ER is synchronous with MRXCLK. When

the encoder/decoder bypass (EDBT) is selected through the MII management interface,

this output serves as the MRXD[4] output.

MTXCLK

Transmit Clock. 25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output in 10 Mbits/s

MII mode, 10 MHz output in 10 Mbits/s serial mode. MTXCLK provides timing reference for

the transfer of the MTX_EN, MTXD, and MTX_ER signals sampled on the rising edge of

MTXCLK.

MTXD[3:0]

Transmit Data. 4-bit parallel input synchronous with MTXCLK. When SER_SEL_PIN is

active-high and 10 Mbits/s mode is selected, only MTXD[0] is valid.

MTX_EN

Transmit Enable. When driven high, this signal indicates there is valid data on MTXD[3:0].

MTX_EN is synchronous with MTXCLK. When SER_SEL_PIN is active-high and

10 Mbits/s mode is selected, this signal indicates there is valid data on MTXD[0].

MTX_ER

Transmit Coding Error. When driven high, this signal causes the encoder to intentionally

corrupt the byte being transmitted across the MII (00100 will be transmitted). When the

encoder/decoder bypass bit is set, this input serves as the MTXD[4] input. When in

10 Mbits/s mode, this signal is ignored.

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