DNC3X3125 datasheet(9/32 Pages) AGERE

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Advance Data Sheet

DNC3X3125

March 2000

10/100 Mbits/s Ethernet Transceiver Macrocell

Signal Information (continued)

Table 5. Clock and Reset Signals

* Double bonded with XLO.

† Double bonded with RMCLK.

Signal

Type

Name/Description

EN_RMCK

Enable RMCLK. When high, this signal selects RMCLK as the clock input.

This signal and EN_XTL cannot be high simultaneously.

RMCLK

PADI*

Primary Input Clock. The frequency of this clock can be either 125 MHz or

50 MHz. IN125 is used to indicate the appropriate frequency. This clock input

is used when EN_RMCK is high.

IN125

Input Clock Frequency Select. When high, this signal will indicate that the

frequency of RMCLK is 125 MHz; else the clock frequency is 50 MHz.

EN_XTL

Enable Crystal Input. This signal, when high, will select the crystal input

(XLO) as the clock input. This signal and EN_RMCK cannot be high simulta-

neously.

EN_NOWR

Enable Nowire Mode. When high, this signal enables NOWIRE logic, which

causes the chip to go into an ultra-low power mode when there is no signalling

from the PHY at the far end of the link.

XLO

PADI†

Crystal Oscillator Input. A 25 MHz crystal ± 25 ppm can be connected

across XLO and XHI. Alternately, a 25 MHz external CMOS oscillator can be

connected to this input. This clock input is used when EN_XTL is high.

XHI

PADO

(optional)

Crystal Oscillator Output. This pad does not have to be bonded out if crystal

is not used.

CLK25RAW

CLK25RAW. 25 MHz output clock.

RMCLKRAW

RMCLKRAW. Buffered version of the RMCLK. This is either 50 MHz or

125 MHz, depending on RMCLK frequency.

SLOWCLK

24 Hz Clock Output. This is a 24 Hz output signal.

HWRESET

Full-Chip Reset. Reset is active-high. The RST_BUSY signal will go low

when reset is complete. 10Base-T and 100Base-TX/-FX are in reset until

enabled and take 1.3 ms to come out of reset. The HWRESET should be a

minimum of 40 nS wide.

POR

Power-On Reset. If a powerup reset (PUR) cell from ASIC library is not used,

then tie this input low.

RST_BUSY

Reset Busy. This signal indicates that the DNC3X3125 is in reset.

RST_10_BUSY

10Base-T in Reset. This signal indicates that the 10 Mbits/s logic is in reset.

RST_TX_BUSY

100Base-TX Reset. This signal indicates that the 100 Mbits/s logic is in reset.

BYPPD125

This pin, when high, powers up the 125 MHz PLL permanently, allowing

CK125P to be used for external logic at all times.

BYPPD160

This pin, when high, powers up the 160 MHz PLL permanently, allowing

CK160 to be used for external logic at all times.

CK125_BUF

This pin is the feedback for CK125P. Normally this will be connected to

CK125P or any external chip clock buffers for CK125P.

CK160

This is a 160 MHz output clock; this will be available if 10Base-T is enabled or

BYPPD160 is high.

CK125P

This is a 125 MHz output clock, which must be fed back to CK125_BUF. This

will be available when in 100Base-Tx mode or if BYPPD125 is high or if IN125

is high.

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