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SPEAR320 Folha de dados(PDF) 9 Page - STMicroelectronics |
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SPEAR320 Folha de dados(HTML) 9 Page - STMicroelectronics |
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9 / 73 page ![]() SPEAr320 Main features Doc ID 16755 Rev 5 9/73 2 Main features ● ARM926EJ-S 32-bit RISC CPU, up to 333 MHz – 16 Kbytes of instruction cache, 16 Kbytes of data cache – 3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code density, byte Java mode (Jazelle™) for direct execution of Java code. – Tightly Coupled Memory ● 32-KByte on-chip BootROM ● 8-KByte on-chip SRAM ● External DRAM memory interface: – 8/16-bit (mobile DDR@166 MHz) – 8/16-bit (DDR2@333 MHz) ● Serial memory interface ● SDIO interface supporting SPI, SD1, SFD4 and SD8 modes ● 8/16-bits NAND Flash controller (FSMC) ● External memory interface (EMI) for connecting NOR Flash or FPGAs ● Boot capability from NAND Flash, serial/parallel NOR Flash ● Boot and field upgrade capability from USB ● High performance 8-channel DMA controller ● 3x Ethernet controllers (up to 2 operating concurrently) ● Two USB2.0 Host (high-full-low speed) with integrated PHY transceiver ● One USB2.0 Device (high-full-low speed) with integrated PHY transceiver ● 2x CAN 2.0 interfaces ● Up to 102 GPIOs with interrupt capability ● Up to 4 PWM outputs ● 3x SSP master/slave (supporting Motorola, Texas instruments, National semiconductor protocols) up to 41.5 Mbps ● Standard parallel port (SPP device implementation) ● 2 x I2C master/slave interface (slow-fast-high speed, up to 1.2 Mb/s) ● 3x UART: – UART0 (up to 3 Mbps) with hardware flow control and modem interface – UART1 (up to 7 Mbps) with hardware flow control (in some operating modes) – UART2 (up to 7 Mbps) with software flow control ● ADC 10-bit, 1 Msps 8 inputs ● JPEG CODEC accelerator 1 clock/pixel ● Color LCD interface (up to 1024X768, 24-bits CLCD controller, TFT and STN panels) ● Touchscreen support ● Crypto accelerator (DES/3DES/AES/SHA1) |
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