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SPEAR320 Folha de dados(PDF) 52 Page - STMicroelectronics |
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SPEAR320 Folha de dados(HTML) 52 Page - STMicroelectronics |
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52 / 73 page ![]() Timing requirements SPEAr320 52/73 Doc ID 16755 Rev 5 7.3.3 DDR2 command timings Figure 8. DDR2 command waveforms Table 30. DDR2 write cycle timings Symbol Description Min Max Unit tDQSS Positive DQS latching edge to associated CK edge -0.5 0.5 ns tDS DQ & DQM output setup time relative to DQS 0 0.25tCK – 0.76 ns tDH DQ & DQM output hold time relative to DQS 0 0.25tCK – 0.84 ns Table 31. DDR2 command timings Symbol Description Min Max Unit tIS Address and control output setup time 0 0.5tCK – 0.5 ns tIH Address and control output hold time 0 0.5tCK – 0.59 ns tIS tIH CLK ADDRESS AND COMMANDS |
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